M368L1624DTL
184pin Unbuffered DDR SDRAM MODULE
128MB DDR SDRAM MODULE
(16Mx64 based on 16Mx16 DDR SDRAM)
Unbuffered 184pin DIMM
64-bit Non-ECC/Parity
Revision 0.1
May. 2002
Rev. 0.1 May. 2002
M368L1624DTL
Revision History
Revision 0 (Jan. 2002)
1. First release for internal usage
184pin Unbuffered DDR SDRAM MODULE
Revision 0.1 (May. 2002)
1.Change pin location of A13 from pin 103 to pin 167
Rev. 0.1 May. 2002
M368L1624DTL
184pin Unbuffered DDR SDRAM MODULE
M368L1624DTL DDR SDRAM 184pin DIMM
16Mx64 DDR SDRAM 184pin DIMM based on 16Mx16
GENERAL DESCRIPTION
The Samsung M368L1624DTL is 16M bit x 64 Double Data
Rate SDRAM high density memory modules.
The Samsung
M368L1624DTL consists of four CMOS 16M x
16 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-
II(400mil) packages mounted on a 184pin glass-epoxy sub-
strate. Four 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each DDR SDRAM.
The M368L1624DTL is Dual In-line Memory Modules and
intended for mounting into 184pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
FEATURE
• Performance range
Part No.
Max Freq.
Interface
SSTL_2
M368L1624DTL-C(L)B3 166MHz(6ns@CL=2.5)
M368L1624DTL-C(L)A2 133MHz(7.5ns@CL=2)
M368L1624DTL-C(L)B0 133MHz(7.5ns@CL=2.5)
• Power supply : Vdd: 2.5V
±
0.2V, Vddq: 2.5V
±
0.2V
•
Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK )
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB :
Height 1250 mil,
double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front
1 VREF
2
DQ0
3
VSS
4
DQ1
5 DQS0
6
DQ2
7
VDD
8
DQ3
9
NC
10
NC
11
VSS
12 DQ8
13 DQ9
14 DQS1
15 VDDQ
16
CK1
17 /CK1
18
VSS
19 DQ10
20 DQ11
21 CKE0
22 VDDQ
23 DQ16
24 DQ17
25 DQS2
26
VSS
27
A9
28 DQ18
29
A7
30 VDDQ
31 DQ19
Pin
Front Pin
Front
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
*/CS2
DQ48
DQ49
VSS
/CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Back
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
*CB4
*CB5
VDDQ
*CK0
*/CK0
VSS
*DM8
A10
*CB6
VDDQ
*CB7
KEY
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
Pin
Back
32
A5
62
33 DQ24 6 3
34
VSS 6 4
35 DQ25 6 5
36 DQS3 6 6
37
A4
67
38
VDD 6 8
39 DQ26 6 9
40 DQ27 7 0
41
A2
71
42
VSS 7 2
43
A1
73
44 *CB0 7 4
45 *CB1 7 5
46
VDD 7 6
47 *DQS8 7 7
48
A0
78
49 *CB2 7 9
50
VSS 8 0
51 *CB3 8 1
52
BA1 8 2
KEY
83
53 DQ32 8 4
54 VDDQ 8 5
55 DQ33 8 6
56 DQS4 8 7
57 DQ34 8 8
58
VSS 8 9
59
BA0 9 0
60 DQ35 9 1
61 DQ40 9 2
154
/RAS
155
DQ45
156 VDDQ
157
/CS0
158
*/CS1
159
DM5
160
VSS
161
DQ46
162
DQ47
163
*/CS3
164 VDDQ
165
DQ52
166
DQ53
167
*A13
168
VDD
169
DM6
170
DQ54
171
DQ55
172 VDDQ
173
NC
174
DQ60
175
DQ61
176
VSS
177
DM7
178
DQ62
179
DQ63
180 VDDQ
181
SA0
182
SA1
183
SA2
184 VDDSPD
PIN DESCRIPTION
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
CK1 ,CK1, CK2, CK2
CKE0
CS0
RAS
CAS
WE
DM0 ~ DM7
VDD
VDDQ
VSS
VREF
VDDSPD
SDA
SCL
SA0 ~ 2
VDDID
NC
*
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
Data Strobe input/output
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Data - in mask
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
Power supply for reference
Serial EEPROM Power
Supply ( 2.3V to 3.6V)
Serial data I/O
Serial clock
Address in EEPROM
VDD identification flag
No connection
These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 May. 2002
M368L1624DTL
FUNCTIONAL BLOCK DIAGRAM
184pin Unbuffered DDR SDRAM MODULE
CS0
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
CS
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
CS
D0
D2
DQS0
DM0
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS4
DM4
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
CS
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D1
DQS6
DM6
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
CS
D3
*Clock Net Wiring
BA0 - BA1
A0 - A13
RAS
CAS
CKE0
WE
BA0-BA1: DDR SDRAMs D0 - D3
A0-A13: DDR SDRAMs D0 - D3
RAS : SDRAMs D0 - D3
CAS : SDRAMs D0 - D3
CKE: SDRAMs D0 - D3
WE: SDRAMs D0 - D3
Clock Wiring
Clock
SDRAMs
Input
CK0/CK0
CK1/CK1
CK2/C K2
NC
2 SDRAMs
2 SDRAMs
Cap
R=120
Ω
Card
Edge
Cap
Dram1
Cap
Dram5
V
DDSPD
V
D D
/V
DDQ
Cap
SPD
D0 - D3
D0 - D3
Serial PD
SCL
WP
A0
SA0
A1
SA1
A2
SA2
SDA
*If two DRAMs are loaded,
Cap will replace DRAM3
VREF
V
SS
D0 - D3
D0 - D3
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 0.1 May. 2002
M368L1624DTL
Absolute Maximum Rate
Parameter
Voltage on any pin relative to V
SS
Voltage on V
D D
& V
DDQ
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
184pin Unbuffered DDR SDRAM MODULE
Symbol
V
I N
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
6
50
Unit
V
V
°C
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 70°C)
Parameter
Supply voltage(for device with a nominal V
DD
of 2.5V)
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input crossing point voltage, CK and CK inputs
Input leakage current
Output leakage current
Output High Current(Normal strengh driver)
;V
OUT
= V
T T
+ 0.84V
Output High Current(Normal strengh driver)
;V
OUT
= V
T T
- 0.84V
Output High Current(Half strengh driver)
;V
OUT
= V
T T
+ 0.45V
Output High Current(Half strengh driver)
;V
OUT
= V
T T
- 0.45V
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
I H
(DC)
V
IL
(DC)
V
I N
(DC)
V
I D
(DC)
V
IX
(DC)
I
I
I
O Z
I
OH
I
OL
I
OH
Min
2.3
2.3
VDDQ/2-50mV
V
REF
-0.04
V
REF
+0.15
-0.3
-0.3
0.3
1.15
-2
-5
-16.8
16.8
-9
Max
2.7
2.7
VDDQ/2+50mV
V
REF
+0.04
V
DDQ
+0.3
V
REF
-0.15
V
DDQ
+0.3
V
DDQ
+0.6
1.35
2
5
Unit
Note
V
V
V
V
V
V
V
V
uA
uA
mA
mA
mA
3
5
1
2
4
4
I
OL
9
mA
Notes
1. Includes
±
25mV margin for DC offset on V
REF
, and a combined total of
±
50mV margin for all AC noise and DC offset on V
REF
,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
REF
and internal DRAM noise coupled
TO V
REF
, both of which may result in V
REF
noise. V
REF
should be de-coupled with an inductance of
≤
3nH.
2.V
TT
is not applied directly to the device. V
T T
is a system supply for signal termination resistors, is expected to be set equal to
V
REF
, and must track variations in the DC level of V
REF
3. V
I D
is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.1 May. 2002