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S1300AAAAS-FREQ(T)

Description
LVCMOS Output Clock Oscillator, 1.5MHz Min, 28.6363MHz Max
CategoryPassive components    oscillator   
File Size3MB,3 Pages
ManufacturerPericom Semiconductor Corporation (Diodes Incorporated)
Websitehttps://www.diodes.com/
Download Datasheet Parametric View All

S1300AAAAS-FREQ(T) Overview

LVCMOS Output Clock Oscillator, 1.5MHz Min, 28.6363MHz Max

S1300AAAAS-FREQ(T) Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum control voltage3 V
Minimum control voltage0.3 V
maximum descent time9 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate50 ppm
frequency stability20%
JESD-609 codee0
linearity5%
Manufacturer's serial numberS1300
Installation featuresSURFACE MOUNT
Maximum operating frequency28.6363 MHz
Minimum operating frequency1.5 MHz
Maximum operating temperature70 °C
Minimum operating temperature
Oscillator typeLVCMOS
Output load30 pF
physical size22mm x 13.4mm x 7.57mm
longest rise time9 ns
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry45/55 %
Terminal surfaceTin/Lead (Sn/Pb)
Base Number Matches1
SaRonix
Voltage Controlled Crystal Oscillator
Technical Data
Frequency Range:
Frequency Stability:
3.3V, LVCMOS
S1300 / S1309 / ST1300 / ST1309 Series
1.5 MHz to 28.6363 MHz
±20, ±25 or ±50ppm over all conditions: operating
temperature, voltage change, load change, calibration
tolerance, shock and vibration, with V
C
= 1.65V
± 3ppm max per year, ±10ppm max for 10 years
Aging @ 25°C:
Temperature Range:
Operating:
Storage:
Supply Voltage:
Recommended Operating:
ACTUAL SIZE
0 to +70°C or -40 to +85°C
-55 to +125°C
3.3V ±10%
10mA typ, 15mA max
Supply Current:
Output Drive:
Description
A 3.3V, voltage controlled crystal oscil-
lator with output logic levels compatible
with LVCMOS and LVTTL logic fami-
lies. The series is designed with excellent
Jitter characteristics which makes it ideal
for use in Telecom and Datacom applica-
tions. True SMD DIL versions for IR
reflow are available, select option "S" in
part number builder. See separate data
sheet for SMD package dimensions.
Applications & Features
Phase-Locked Loop (PLL) Clock and
Data Recovery, Frequency Transaltion,
Frequency Synthesis apps in Video,
Video Compression, Telephony, and
LAN/WAN Data Communication
3.3 Volt operations
LVCMOS / LVTTL compatible
3.5ps max RMS period jitter
Wide range of performance options:
±50 to ±100 ppm APR*
±20 to ±50 ppm Frequency Stability
Tri-State option
True SMD for IR reflow available
Output Waveform
CMOS
T
r
Logic 1
80%V
DD
50%V
DD
20%V
DD
Logic 0
T
f
Symmetry:
Rise & Fall Times:
Logic 0:
Logic 1:
Load:
Jitter:
Pull Characteristics:
Input Impedance (pin 1):
Frequency Response (-3dB):
Pullability:
Control Voltage:
Transfer Function:
Linearity:
Center Control Voltage:
Mechanical:
Shock:
Solderability:
Terminal Strength:
Vibration:
Solvent Resistance:
Resistance to Soldering Heat:
Environmental:
Gross Leak Test:
Fine Leak Test:
Thermal Shock:
Moisture Resistance:
45/55% max @ 50% V
DD
9ns max 20% to 80% V
DD
10% V
DD
max
90% V
DD
min
30pF
3.5ps max RMS period jitter
50KΩ min
10 kHz min
±50, ±70, ±100ppm APR* min
0.3 to 3.0V
Frequency Increases when Control Voltage Increases
5 or 10% max
1.65V
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 2003
MIL-STD-883, Method 2004, Condition B2
MIL-STD-883, Method 2007, Condition A
MIL-STD-202, Method 215
MIL-STD-202, Method 210, Conditions A, B or C
( I or J for Gull Wing)
MIL-STD-883C,
MIL-STD-883C,
MIL-STD-883C,
MIL-STD-883C,
Method
Method
Method
Method
1014, Condition C
1014, Condition A2
1011, Condition A
1004
*
APR = (VCXO Pull relative to specified Output Frequency)
(VCXO Frequency Stability)
NOTE: APR is inclusive of 10 Years Aging
SYMMETRY
DS-126
REV E
SaRonix
www.pericom.com/saronix
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