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M12S16161A-7BIG

Description
Synchronous DRAM, 1MX16, 6ns, CMOS, PBGA60, 6.40 X 10.10 MM, 0.65 MM PITCH, LEAD FREE, VFBGA-60
Categorystorage    storage   
File Size622KB,30 Pages
ManufacturerESMT
Websitehttp://www.esmt.com.tw/
Elite Semiconductor Memory Technology Inc. (ESMT) is a professional IC design company founded by Dr. Hu Zhao in June 1998. Its headquarters is located in Hsinchu Science Park, Taiwan. The company's main business includes research, development, manufacturing, sales and related technical services of IC products. It was listed on the Taiwan Stock Exchange in March 2002.
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M12S16161A-7BIG Overview

Synchronous DRAM, 1MX16, 6ns, CMOS, PBGA60, 6.40 X 10.10 MM, 0.65 MM PITCH, LEAD FREE, VFBGA-60

M12S16161A-7BIG Parametric

Parameter NameAttribute value
Parts packaging codeBGA
package instructionVFBGA,
Contacts60
Reach Compliance Codeunknown
ECCN codeEAR99
access modeDUAL BANK PAGE BURST
Maximum access time6 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PBGA-B60
length10.1 mm
memory density16777216 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals60
word count1048576 words
character code1000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize1MX16
Package body materialPLASTIC/EPOXY
encapsulated codeVFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, VERY THIN PROFILE, FINE PITCH
Certification statusNot Qualified
Maximum seat height1 mm
self refreshYES
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal pitch0.65 mm
Terminal locationBOTTOM
width6.4 mm
Base Number Matches1

M12S16161A-7BIG Preview

Download Datasheet
ESMT
SDRAM
M12S16161A
Operation Temperature Condition -40°C~85°C
512K x 16Bit x 2Banks
Synchronous DRAM
FEATURES
JEDEC standard 2.5V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-
CAS Latency (2 & 3 )
-
Burst Length (1, 2, 4, 8 & full page)
-
Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
32ms refresh period (2K cycle)
GENERAL DESCRIPTION
The M12S16161A is 16,777,216 bits synchronous high
data rate Dynamic RAM organized as 2 x 524,288 words by
16 bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
ORDERING INFORMATION
Part NO.
M12S16161A-6TIG
M12S16161A-7TIG
M12S16161A-6BIG
M12S16161A-7BIG
MAX Freq.
166MHz
143MHz
166MHz
143MHz
PACKAGE COMMENTS
TSOP(II)
TSOP(II)
VFBGA
VFBGA
Pb-free
Pb-free
Pb-free
Pb-free
PIN CONFIGURATION (TOP VIEW)
1
A
VSS
2
DQ15
3
4
5
6
DQ0
7
VDD
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V
SS
50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
B
DQ14
VSSQ
VDDQ
DQ1
C
DQ13
VDDQ
VSSQ
DQ2
D
DQ12
DQ11
DQ4
DQ3
E
DQ10
VSSQ
VDDQ
DQ5
F
DQ9
VDDQ
VSSQ
DQ6
G
DQ8
NC
NC
DQ7
H
NC
NC
NC
NC
J
NC
UDQM
LDQM
WE
K
NC
CLK
RAS
CAS
L
CKE
NC
NC
CS
M
BA
A9
NC
NC
N
A8
A7
A0
A10
P
A6
A5
A2
A1
60 Ball VFBGA
(6.4x10.1mm)
(0.65mm ball pitch)
R
VSS
A4
A3
VDD
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Sep. 2007
Revision
:
1.0
1/30
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