SLA507T datasheet, PDF - EEWORLD Datasheet

SLA507T: DescriptionFPGA, 64407 GATES, UUC144, TCP-144; CategoryProgrammable logic devices Programmable logic; File Size58KB，1 Pages; ManufacturerSeiko Epson Corporation

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SLA507T Overview

FPGA, 64407 GATES, UUC144, TCP-144

Parameter Name	Attribute value
Parts packaging code	DIE
package instruction	DIE,
Contacts	144
Reach Compliance Code	unknown
Other features	WITH 2.0V SUPPLY VOLTAGE
Combined latency of CLB-Max	0.14 ns
JESD-30 code	X-XUUC-N144
Equivalent number of gates	64407
Number of terminals	144
organize	64407 GATES
Package body material	UNSPECIFIED
encapsulated code	DIE
Package shape	UNSPECIFIED
Package form	UNCASED CHIP
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Terminal form	NO LEAD
Terminal location	UPPER
Base Number Matches	1

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

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