HD74LS193
Synchronous Up / Down Decade Counter (dual clock lines)
REJ03D0455–0200
Rev.2.00
Feb.18.2005
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the output change
coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output
counting spikes, which are normally associated with asynchronous (ripple clock) counters. The outputs of the four
master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of
counting is determined by which count input is pulsed while the other count input is high. This counter is fully
programmable; that is, each output may be preset to either level by entering the desired data at the data inputs while the
load inputs is low. The output will change to agree with the data inputs independently of the count pulses. This feature
allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A
clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function
is independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive
requirements. This reduces the number of clock drivers, etc., required for long words. This counter was designed to be
cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up-
and down-counting functions.
The borrow output produces a pulse equal in width to the count-down input when the counter underflows. Similarly,
the carry output produces a pulse equal in width to the count up input when an overflow condition exists.
The counters can be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs
respectively of .the succeeding counter.
Features
•
Ordering Information
Part Name
HD74LS193P
HD74LS193FPEL
HD74LS193RPEL
Package Type
DILP-16 pin
SOP-16 pin (JEITA)
SOP-16 pin (JEDEC)
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
PRSP0016DH-B
(FP-16DAV)
PRSP0016DG-A
(FP-16DNV)
Package
Abbreviation
P
FP
RP
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Note: Please consult the sales office for the above package availability.
Rev.2.00, Feb.18.2005, page 1 of 11
HD74LS193
Recommended Operating Conditions
Item
Supply voltage
Output current
Operating temperature
Clock frequency
Pulse width
Setup time (Clear)
Setup time
Hold time
Symbol
V
CC
I
OH
I
OL
T
opr
ƒ
clock
t
w
t
su (CLR)
t
su
t
h
Min
4.75
—
—
–20
0
20
40
20
3
Typ
5.00
—
—
25
—
—
—
—
—
Max
5.25
–400
8
75
25
—
—
—
—
Unit
V
µA
mA
°C
MHz
ns
ns
ns
ns
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Input voltage
Symbol
V
IH
V
IL
V
OH
Output voltage
V
OL
I
IH
I
IL
I
I
Short-circuit output
current
Supply current**
Input clamp voltage
I
OS
I
CC
V
IK
min.
2.0
—
2.7
—
—
—
—
—
–20
—
—
typ.*
—
—
—
—
—
—
—
—
—
19
—
max.
—
0.8
—
0.4
0.5
20
–0.4
0.1
–100
34
–1.5
Unit
V
V
V
V
µA
mA
mA
mA
mA
V
Condition
V
CC
= 4.75 V, V
IH
= 2 V, V
IL
= 0.8 V,
I
OH
= –400
µA
I
OL
= 4 mA
V
CC
= 4.75 V, V
IH
= 2 V,
V
IL
= 0.8 V
I
OL
= 8 mA
V
CC
= 5.25 V, V
I
= 2.7 V
V
CC
= 5.25 V, V
I
= 0.4 V
V
CC
= 5.25 V, V
I
= 7 V
V
CC
= 5.25 V
V
CC
= 5.25 V
V
CC
= 4.75 V, I
IN
= –18 mA
Input current
Notes: * V
CC
= 5 V, Ta = 25°C
** I
CC
is measured with all outputs open, clear and load inputs grounded, and all other inputs at 4.5 V.
Switching Characteristics
(V
CC
= 5 V, Ta = 25°C)
Item
Maximum clock frequency
Symbol
ƒ
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
Inputs
Outputs
min.
25
—
—
—
—
—
—
—
—
—
typ.
32
17
18
16
15
27
30
24
25
23
max.
—
26
24
24
24
38
47
40
40
35
Unit
MHz
ns
ns
ns
ns
ns
Condition
Count-up
Count-down
Either Count
Load
Clear
Carry
Borrow
Q
Q
Q
Propagation delay time
C
L
= 15 pF,
R
L
= 2 kΩ
Rev.2.00, Feb.18.2005, page 4 of 11
HD74LS193
Count Sequences
Clear
Load
A
Data
Inputs
B
C
D
Count Up
Count Down
Q
A
Q
B
Outputs
Q
C
Q
D
Carry
Borrow
14
0
13
15
0
1
2
1
0
15
14
13
Count Up
Count Down
Clear Preset
Illustrated below is the following sequence:
1. Clear outputs to zero.
2. Load (preset) to binary thirteen.
3. Count up to fourteen, fifteen, carry, zero, one and two.
4. Count down to one, zero, borrow, fifteen, fourteen, and thirteen.
Rev.2.00, Feb.18.2005, page 5 of 11