HD74LS162A
Synchronous Decade Counter (synchronous clear)
REJ03D0446–0300
Rev.3.00
Jul.15.2005
This synchronous decade counter features an internal carry look-ahead for application in high-speed counting designs.
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes
coincident with each other when so instructed by the count-enable inputs and internal gating. This mode is operation
eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This
counter is fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting
up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next
clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input should be avoided
when the clock is low if the enable inputs are high at or before the transition. The clear function is asynchronous and a
low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of
the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum
count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to
synchronously clear the counter to LLLL. Low-to-high transitions at the clear input should be avoided when the clock
is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for
cascading counters for n-bit synchronous applications without additional getting. Instrumental in accomplishing this
function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to
count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a
high-level output pulse with a duration approximately equal to the high-level portion of the Q
A
output. This high-level
overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low-level transitions at the
enable P or T inputs should occur only when the clock input is high.
Features
•
Ordering Information
Part Name
HD74LS162AFPEL
Package Type
SOP-16 pin (JEITA)
Package Code
(Previous Code)
PRSP0016DH-B
(FP-16DAV)
Package
Abbreviation
FP
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
Rev.3.00, Jul.15.2005, page 1 of 10
HD74LS162A
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
P
T
Tstg
Ratings
7
7
400
–65 to +150
Unit
V
V
mW
°C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Supply voltage
Output current
Operating temperature
Clock frequency
Clock pulse width
Clear pulse width
A, B, C, D
Setup time
Enable P, T
Load
Clear
Hold time
t
h
t
su
Symbol
V
CC
I
OH
I
OL
Topr
ƒ
clock
t
w (clock)
t
w (clear)
Min
4.75
—
—
–20
0
25
20
20
20
20
20
3
Typ
5.00
—
—
25
—
—
—
—
—
—
—
—
Max
5.25
–400
8
75
25
—
—
—
—
—
—
—
Unit
V
µA
mA
°C
MHz
ns
ns
ns
ns
ns
ns
ns
Typical Clear, Preset, and Inhibit Sequence
Clear
Load
A
Data
Inputs
B
C
D
Clock
Enable P
Enable T
Q
A
Q
B
Outputs
Q
C
Q
D
Ripple Carry
Output
7
Preset
(Load)
8
9
0
1
Count
2
Inhibit
Clear
Rev.3.00, Jul.15.2005, page 3 of 10
HD74LS162A
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Input voltage
Symbol
V
IH
V
IL
V
OH
Output voltage
V
OL
Data, Enable P
Load, Clock, Enable T
Clear
Data, Enable P
Load, Clock, Enable T
Clear
Data, Enable P
Load, Clock, Enable T
min.
2.0
—
2.7
—
—
—
—
—
—
—
—
—
—
—
–20
—
—
—
typ.*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18
19
—
max.
—
0.8
—
0.4
0.5
20
40
40
–0.4
–0.8
–0.8
0.1
0.2
0.2
–100
31
32
–1.5
Unit
V
V
V
V
Condition
V
CC
= 4.75 V, V
IH
= 2 V, V
IL
= 0.8 V,
I
OH
= –400
µA
I
OL
= 4 mA V
CC
= 4.75 V, V
IH
= 2 V,
I
OL
= 8 mA V
IL
= 0.8 V
V
CC
= 5.25 V, V
I
= 2.7 V
I
IH
µA
Input
current
I
IL
mA
V
CC
= 5.25 V, V
I
= 0.4 V
I
I
I
OS
I
CCH
I
CCL
V
IK
mA
mA
mA
mA
V
V
CC
= 5.25 V, V
I
= 7 V
V
CC
= 5.25 V
V
CC
= 5.25 V
V
CC
= 5.25 V
V
CC
= 4.75 V, I
IN
= –18 mA
Clear
Short-circuit output current
Supply current**
Input clamp voltage
Notes: * V
CC
= 5 V, Ta = 25°C
** I
CCH
is measured with the load input high, then again with the load input low, with all other inputs high and all
outputs open. I
CCL
is measured with the clock input high, then again with the clock input low, with all other
inputs low and all outputs open.
Switching Characteristics
(V
CC
= 5 V, Ta = 25°C)
Item
Maximum clock frequency
Symbol
ƒ
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
Inputs
Clock
Clock
Clock
(Load = “H”)
Clock
(Load = “L”)
Enable T
Clear
Outputs
Q
A
to Q
D
Ripple
Carry
Q
A
to Q
D
Q
A
to Q
D
Ripple
Carry
Q
A
to Q
D
min.
25
—
—
—
—
—
—
—
—
—
typ.
32
20
18
13
18
13
18
9
9
20
max.
—
35
35
24
27
24
27
14
14
28
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Condition
Propagation delay time
C
L
= 15 pF,
R
L
= 2 kΩ
Rev.3.00, Jul.15.2005, page 4 of 10
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