L6743
L6743Q
High current MOSFET driver
Features
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■
■
■
■
■
■
■
■
■
Dual MOSFET driver for synchronous rectified
converters
High driving current for fast external MOSFET
switching
Integrated bootstrap diode
High frequency operation
Enable pin
Adaptive dead-time management
Flexible gate-drive: 5 V to 12 V compatible
High-impedance (HiZ) management for output
stage shutdown
Preliminary OV protection
SO-8 and DFN10 3x3 packages
SO-8
DFN10 3x3
Combined with ST PWM controllers, the driver
allows implementing complete voltage regulator
solutions for modern high-current CPUs and
DCDC conversion in general. L6743, L6743Q
embeds high-current drivers for both high-side
and low-side MOSFETS. The device accepts
flexible power supply (5 V to 12 V) to optimize the
gate-drive voltage for High-Side and Low-Side
maximizing the System Efficiency.
The Bootstrap diode is embedded saving the use
of external diodes. Anti shoot-through
management avoids high-side and low-side
MOSFET to conduct simultaneously and,
combined with Adaptive Dead-Time control,
minimizes the LS body diode conduction time.
L6743, L6743Q embeds Preliminary OV
Protection: after Vcc overcomes the UVLO and
while the device is in HiZ, the LS MOSFET is
turned ON to protect the load in case the output
voltage overcomes a warning threshold protecting
the output against HS failures.
The driver is available is SO-8 and DFN10 3x3
packages
Applications
■
■
High current VRM / VRD for desktop / server /
workstation CPUs
High current and high efficiency DC / DC
converters
Description
L6743, L6743Q is a flexible, high-frequency dual-
driver specifically designed to drive N-channel
MOSFETs connected in synchronous-rectified
buck topology.
Table 1.
Device summary
Order code
L6743
L6743TR
L6743Q
L6743QTR
Package
SO-8
SO-8
DFN10
DFN10
Packaging
Tube
Tape and reel
Tube
Tape and reel
June 2008
Rev 2
1/17
www.st.com
1
Contents
L6743, L6743Q
Contents
1
Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.1
4.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.1
5.2
5.3
5.4
5.5
High-impedance (HiZ) management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Preliminary OV protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Internal BOOT diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
L6743, L6743Q
Typical application circuit and block diagram
1
1.1
Typical application circuit and block diagram
Application circuit
Figure 1.
Typical application circuit
V
CC
= 5V to 12V
C
DEC
VCC
BOOT
C
HF
PWM Input
C
BULK
V
IN
= 5V to 12V
L6743
PWM
UGATE
HS
L
Vout
EN Input
EN
PHASE
GND
NC*
L6743 Reference Schematic
LGATE
NC*
LS
C
OUT
1.2
Block diagram
Figure 2.
Block diagram
VCC
EN
ADAPTIVE ANTI
CROSS CONDUCTION
15k
GND
HS
BOOT
UGATE
PHASE
VCC
L6743
PWM
CONTROL LOGIC
& PROTECTIONS
PWM
LS
LGATE
GND
3/17
Pin description and connection diagrams
L6743, L6743Q
2
Pin description and connection diagrams
Figure 3.
Pin connection (top view)
1
2
3
4
8
BOOT
PWM
EN
VCC
L6743
7
6
5
UGATE
PHASE
GND
LGATE
BOOT
PWM
EN
VCC
VCC
1
2
3
4
5
10
9
L6743Q
8
7
6
UGATE
PHASE
GND
GND
LGATE
2.1
Table 2.
Pin n
Pin description
Pin description
Name
Function
High-side driver supply.
This pin supplies the high-side floating driver. Connect through a R
BOOT
- C
BOOT
capacitor to the PHASE pin.
Internally connected to the cathode of the integrated bootstrap diode. See
Section 5.3
for guidance in designing the capacitor value.
Control input for the driver, 5 V compatible.
This pin controls the state of the driver and which external MOSFET have to be
turned-ON according to EN status. If left floating and in conjunction with EN
asserted, it causes the driver to enter the high-impedance (HiZ) state which causes
all MOSFETs to be OFF. See
Section 5.1
for details about HiZ.
Enable input for the driver. Internally pulled low by 15 kΩ.
Pull high to enable the driver according to the PWM status. If pulled low will cause
the drive to enter HiZ state with all MOSFET OFF regardless of the PWM status.
See
Section 5.1
for details about HiZ.
Device and LS driver power supply. Connect to any voltage between 5 V and 12 V.
Bypass with low-ESR MLCC capacitor to GND.
Low-side driver output.
Connect directly to the low-side MOSFET gate. A small series resistor can be useful
to reduce dissipated power especially in high frequency applications.
All internal references, logic and drivers are referenced to this pin. Connect to the
PCB ground plane.
High-side driver return path. Connect to the high-side MOSFET source.
This pin is also monitored for the adaptive dead-time management and Pre-OV
Protection.
High-side driver output.
Connect to high-side MOSFET gate.
Thermal pad connects the Silicon substrate and makes good thermal contact with
the PCB. Connect to the PGND plane. (DFN10 only)
DFN10
SO-8
1
1
BOOT
2
2
PWM
3
3
EN
4, 5
4
VCC
6
5
LGATE
7, 8
6
GND
9
7
PHASE
10
PAD
8
-
UGATE
TH. PAD
4/17
L6743, L6743Q
Thermal data
3
Thermal data
Table 3.
Symbol
Thermal data
Value
Parameter
SO8
DFN10
45
5
150
0 to 150
0 to 125
1.15
2.25
°C/W
°C/W
°C
°C
°C
W
Thermal resistance junction to ambient
(Device soldered on 2s2p, 67 mm x 69 mm board)
Thermal resistance junction to case
Maximum junction temperature
Storage temperature range
Junction temperature range
Maximum power dissipation at 25°C
(Device soldered on 2s2p PC board)
Unit
R
thJA
R
thJC
T
MAX
T
STG
T
J
P
TOT
85
-
4
4.1
Electrical specifications
Absolute maximum ratings
Table 4.
Symbol
V
CC,
V
PVCC
V
BOOT
, V
UGATE
V
PHASE
V
LGATE
V
PWM,
V
EN
V
CC,
V
PVCC
to GND
to GND
to PHASE
to GND
to GND
to GND
to GND
Absolute maximum ratings
Parameter
Value
-0.3 to 15
41
15
-8 to 26
-0.3 to VCC + 0.3
-0.3 to 7
-0.3 to 15
Unit
V
V
V
V
V
V
5/17
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