A63P0636
1M X 36 Bit Synchronous High Speed SRAM with
Preliminary
Features
Fast access times: 2.6/2.8/3.2/3.5/3.8/4.2
(250/227/200/166/150/133 MH
Z
)
Single +2.5V+10% or +2.5V-5% power supply
Synchronous burst function
Individual Byte Write control and Global Write
Registered output for pipelined applications
ns
Three separate chip enables allow wide range of
options for CE control, address pipelining
Selectable BURST mode
SLEEP mode (ZZ pin) provided
Available in 100-pin LQFP package
Burst Counter and Pipelined Data Output
General Description
The A63P0636E is a high-speed SRAM containing 36M
bits of bit synchronous memory, organized as 1024K
words by 36 bits.
The A63P0636E combines advanced synchronous
peripheral circuitry, 2-bit burst control, input registers,
output registers and a 1MX36 SRAM core to provide a
wide range of data RAM applications.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. Synchronous inputs include all addresses (A0 -
A19), all data inputs (I/O
1
- I/O
36
), active LOW chip enable
(
CE ), two additional chip enables (CE2, CE2 ), burst
control inputs ( ADSC , ADSP , ADV ), byte write enables
( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write
( GW ). Asynchronous inputs include output enable ( OE ),
clock (CLK), BURST mode (MODE) and SLEEP mode
(ZZ).
Burst operations can be initiated with either the address
status processor ( ADSP ) or address status controller
( ADSC ) input pin. Subsequent burst sequence burst
addresses can be internally generated by the A63P0636E
and controlled by the burst advance ( ADV ) pin. Write
cycles are internally self-timed and synchronous with the
rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte
enables allow individual bytes to be written. BW1 controls
I/O
1
- I/O
9
, BW2 controls I/O
10
- I/O
18
, BW3 controls
I/O
19
- I/O
27
, and BW4 controls I/O
28
- I/O
36
, all on the
condition that BWE is LOW. GW LOW causes all bytes
to be written.
PRELIMINARY
(July, 2005, Version 0.0)
1
AMIC Technology, Corp.
A63P0636
Pin Description
Pin No.
Symbol
Description
32 – 37,39, 44 - 50, 81,
82, 99, 100
89
87, 93 - 96
88
86
92, 97, 98
83
84
85
31
A0 - A19
Address Inputs
CLK
BWE , BW1 - BW4
GW
OE
CE2 ,CE2, CE
ADV
ADSP
ADSC
MODE
Clock
Byte Write Enables
Global Write
Output Enable
Chip Enables
Burst Address Advance
Processor Address Status
Controller Address Status
Burst Mode: HIGH or NC (Interleaved burst)
LOW (Linear burst)
Asynchronous Power-Down (Snooze): HIGH (Sleep)
LOW or NC (Wake up)
Data Inputs/Outputs
64
ZZ
1,2, 3, 6 - 9, 12, 13, 18,
19, 22 - 25, 28, 29,
30,51,52, 53,
56 - 59, 62, 63, 68, 69, 72
- 75, 78, 79,80
15, 41, 65, 91
17, 40, 67, 90
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 21, 26,
55, 60, 71, 76
I/O
1
- I/O
36
VCC
GND
VCCQ
Power Supply
Ground
Isolated Output Buffer Supply
GNDQ
Isolated Output Buffer Ground
PRELIMINARY
(July, 2005, Version 0.0)
4
AMIC Technology, Corp.
京公网安备 11010802033920号
EEWORLD
