Intel
®
IXF3204 Quad T1/E1/J1 Framer
with Intel
®
On-Chip PRM
Datasheet
Product Features
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Quad T1/E1/J1 Framer
Software selectable and fully independent
T1/E1/J1 operation
Support for T1/E1/J1 standards:
— T1: T1-SF, T1-ESF, Lucent* SLC
®
96
— E1: PCM30, G.704, G.706, G.732 ISDN
PRI
— J1: J1-SF and J1-ESF
Programmable transmit/receive slip buffers
On-chip Intel
®
Performance Report
Messaging per ANSI T1.231, T1.403, and
ITU G.826
24 fully independent HDLC controllers
with 128-byte transmit/receive FIFOs
support GR-303 and V5.1/5.2 standards
FDL Support:
— DL support for ESF per ANSI T1.403 or
AT&T* TR54016 (T1/J1)
— DDL bit access for Lucent SLC
®
96
— Sa bit access for E1
256-PBGA package, 17 mm x 17 mm
Operating temperature -40
°C
to 85
°C
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Diagnostics:
— BERT generators and analyzers for
extensive on-chip error testing at DS-0,
DS-1, and E1 rates
— Pseudo-random and programmable bit-
sequence generator and monitoring
— Per-link diagnostics and loopbacks
Programmable system backplane data rates
at 1x/2x/4x/8x of T1/E1 data rates for
support of MVIP, H-MVIP, H.100, and CHI
Support for fractional T1/E1
Signaling:
— Support for T1/E1 CAS and T1/E1 CCS
— Signaling state-change indication
— Signaling freeze/debounce per DS-1
— Signaling force per DS-0
Red/Yellow/AIS alarm indication
Intel
®
/Motorola* 8-bit processor interface
Industry-standard P1149.1 JTAG test port
Low-power 1.8/3.3-V CMOS technology
with 5-V tolerant I/Os
Applications
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Integrated Multi-service Access Platforms
(IMAPs)
Integrated Access Devices (IADs)
Inverse Multiplexing for Asynchronous
Transfer Mode (also known as ‘IMA’)
Frame-relay access devices
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Channel service unit (CSU) / Data Service
Unit (DSU) equipment
Wireless base stations, radio network
controllers
Routers
Document Number: 278594
Revision Number: 003
Revision Date: December 2, 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel
®
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems,
or in nuclear facility applications
.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
IXF3204 OctalQuad T1/E1/J1 Framer with Intel
®
On-Chip PRM may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-
548-4725, or by visiting Intel's website at http://www.intel.com.
*Other names and brands may be claimed as the property of others.
Copyright © Intel Corporation 2003.
2
Datasheet
Document Number: 278594
Revision Number: 003
Revision Date: December 2, 2003
Contents
Contents
1.0
2.0
Introduction to Document
..................................................................................... 19
Product Summary
.................................................................................................... 20
2.1
2.2
2.3
Description .......................................................................................................... 20
Conventions and Terminology............................................................................. 24
2.2.1 Conventions and Terminology for T1/E1................................................ 24
2.2.2 Conventions and Nomenclature for Intel
®
IXF3204 Framer ................... 25
Related Documents............................................................................................. 25
Signal Groupings................................................................................................. 26
Ball Descriptions.................................................................................................. 27
3.2.1 Ball Descriptions - Interface to Line Interface Unit ................................. 27
3.2.2 Ball Descriptions - Interface to System Backplane Bus ......................... 29
3.2.3 Ball Descriptions - Interface to Host Processor...................................... 32
3.2.4 Ball Descriptions - Clock and Clock References .................................... 33
3.2.5 Ball Descriptions - Test Interfaces.......................................................... 34
3.2.6 Ball Descriptions - Power and Grounds ................................................. 35
3.2.7 Ball Descriptions - No Connects............................................................. 36
Feature Set.......................................................................................................... 37
Indicators............................................................................................................. 49
Initialization.......................................................................................................... 53
Reset ................................................................................................................... 53
Interrupt Handling................................................................................................ 53
5.3.1 Interrupt Handling - Events Related to Framer Ports ............................. 54
5.3.2 Interrupt Handling - Events Related to HDLC and BERT.......................55
T1 Line Coding .................................................................................................... 57
6.1.1 T1 Alternate Mark Inversion ................................................................... 57
6.1.2 T1 Zero Code Suppression .................................................................... 58
6.1.3 T1 Binary Eight Zero Substitution........................................................... 58
T1 Line Monitoring............................................................................................... 59
6.2.1 T1 Alarm Indication Signal ..................................................................... 59
6.2.2 T1 Bipolar Violations .............................................................................. 59
6.2.3 T1 Excess Zeroes .................................................................................. 59
6.2.4 T1 Loss of Signal.................................................................................... 60
T1 Insertion of Line Errors................................................................................... 60
T1 Framing .......................................................................................................... 61
T1 Superframe .................................................................................................... 62
6.5.1 T1 SF Mode Description......................................................................... 62
6.5.2 T1 SF Framing Algorithm ....................................................................... 63
T1 SLC
®
96 Mode ................................................................................................ 64
3
3.0
Signal Descriptions
................................................................................................. 26
3.1
3.2
4.0
Feature Set and Indicators
................................................................................... 37
4.1
4.2
5.0
Initialization, Reset, and Interrupts
................................................................... 53
5.1
5.2
5.3
6.0
T1 Framers
.................................................................................................................. 56
6.1
6.2
6.3
6.4
6.5
6.6
Datasheet
Document Number: 278594
Revision Number: 003
Revision Date: December 2, 2003
Contents
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.6.1 T1 SLC
®
96 Description .......................................................................... 64
6.6.2 T1 SLC
®
96 Framing Algorithm............................................................... 67
T1 Extended SuperFrame ................................................................................... 68
6.7.1 T1 ESF Description ................................................................................ 68
6.7.2 T1 ESF CRC-6 Procedures.................................................................... 68
6.7.3 T1 ESF Framing Algorithm..................................................................... 69
T1 General Framing Properties........................................................................... 72
6.8.1 T1 False Framing Protection .................................................................. 72
6.8.2 T1 Maximum Average Reframe Time .................................................... 72
T1 Framing Indicators ......................................................................................... 73
6.9.1 T1 Frame Bit Error ................................................................................. 73
6.9.2 T1 Out-of-Frame Detection .................................................................... 73
6.9.3 T1 Resynchronization ............................................................................ 73
6.9.4 T1 Change Of Frame Alignment ............................................................ 73
T1 Frame and Cyclic Redundancy Check Error Insertion ................................... 74
6.10.1 T1 Frame Bit Error Insertion................................................................... 74
6.10.2 T1 CRC Error Insertion........................................................................... 74
T1 Alarm Overview.............................................................................................. 75
T1 Red Alarm ...................................................................................................... 75
T1 Yellow Alarm .................................................................................................. 76
6.13.1 T1 Yellow Alarm Detection ..................................................................... 76
6.13.2 T1 Yellow Alarm Transmission............................................................... 76
T1 Blue Alarm ..................................................................................................... 77
6.14.1 T1 Blue Alarm Detection ........................................................................ 77
6.14.2 T1 Blue Alarm Transmission .................................................................. 77
Fractional T1 ....................................................................................................... 77
J1 Frame Operations .......................................................................................... 78
7.1.1 J1 Frame Operation - Modified 12-Frame Multiframe ............................ 79
7.1.2 J1 Frame Operation - Modified 24-Frame Multiframe ............................ 80
J1 Alarm Overview .............................................................................................. 81
J1 Yellow Alarm .................................................................................................. 81
7.3.1 J1 Yellow Alarm Detection ..................................................................... 81
7.3.2 J1 Yellow Alarm Transmission ............................................................... 81
E1 Line Coding.................................................................................................... 83
8.1.1 E1 Alternate Mark Inversion ................................................................... 83
8.1.2 E1 High-Density Bipolar Three............................................................... 83
E1 Line Monitoring .............................................................................................. 84
8.2.1 E1 Alarm Indication Signal ..................................................................... 84
8.2.2 E1 Auxiliary Pattern................................................................................ 84
8.2.3 E1 Coding Violations .............................................................................. 85
8.2.4 E1 Loss of Signal ................................................................................... 85
E1 Insertion of Line Errors .................................................................................. 85
E1 Framing.......................................................................................................... 86
E1 FAS/NFAS Framing ....................................................................................... 86
8.5.1 E1 FAS/NFAS Framing Description ....................................................... 86
8.5.2 E1 FAS/NFAS Framing Operation ......................................................... 88
7.0
J1 Framers
.................................................................................................................. 78
7.1
7.2
7.3
8.0
E1 Framers
.................................................................................................................. 82
8.1
8.2
8.3
8.4
8.5
4
Datasheet
Document Number: 278594
Revision Number: 003
Revision Date: December 2, 2003
Contents
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
8.5.3 E1 FAS/NFAS Error Generation............................................................. 88
E1 CRC-4 Multiframe .......................................................................................... 89
8.6.1 E1 CRC-4 Multiframe Description .......................................................... 89
8.6.2 E1 CRC-4 Multiframe Operation ............................................................ 90
8.6.3 E1 CRC-4 Multiframe Interworking......................................................... 90
8.6.4 E1 CRC-4 Multiframe Error Checking ....................................................90
8.6.5 E1 Loss of CRC-4 Multiframe Alignment................................................ 90
8.6.6 E1 CRC-4 Multiframe Transmission ....................................................... 91
8.6.7 E1 CRC-4 Error Insertion ....................................................................... 91
E1 Remote End Block Error Operation ............................................................... 91
E1 Channel-Associated Signaling Multiframe ..................................................... 92
8.8.1 E1 CAS Multiframe Description.............................................................. 92
8.8.2 E1 CAS Multiframe Operation ................................................................ 93
8.8.3 E1 Loss of CAS Multiframe .................................................................... 93
8.8.4 E1 CAS Multiframe Transmission .......................................................... 93
8.8.5 E1 CAS Multiframe Alignment to FAS/NFAS ......................................... 93
E1 Simultaneous CAS and CRC Multiframes ..................................................... 94
E1 Alarm Overview..............................................................................................95
E1 Alarm: Red Alarm........................................................................................... 95
E1 Alarm: Remote Alarm Indication .................................................................... 95
E1 Alarm: TS16 RAI ............................................................................................ 96
E1 Alarm: TS16 AIS ............................................................................................ 96
E1 Alarm: AIS...................................................................................................... 97
E1 Main Indicators............................................................................................... 98
8.16.1 E1 Loss of Basic Frame Alignment - FAS/NFAS ................................... 98
8.16.2 E1 Loss of CRC Alignment..................................................................... 98
8.16.3 E1 Loss of CAS Multiframe Alignment ................................................... 99
8.16.4 E1 Change of Frame Alignment ............................................................. 99
8.16.5 E1 FAS and NFAS Error Counting ......................................................... 99
8.16.6 E1 CRC Error Counting.......................................................................... 99
E1 Receiver Resynchronization Control.............................................................. 99
E1 Sa/Si Bit Access and Handling ....................................................................100
8.18.1 E1 Sa/Si Bit Reception and Codewords...............................................100
8.18.2 E1 Sa/Si Transmission and Codewords...............................................101
Fractional E1 Mode ...........................................................................................101
9.0
10.0
Unframed Mode
.......................................................................................................102
Signaling
....................................................................................................................103
10.1
10.2
Signaling Overview............................................................................................103
Channel-Associated Signaling ..........................................................................104
10.2.1 T1 Channel-Associated (Robbed-Bit) Signaling...................................104
10.2.2 T1 Channel-Associated Signaling: Per Time-Slot Enable ....................105
10.2.3 E1 Channel-Associated Signaling: Time Slot 16..................................106
10.2.4 E1 Channel-Associated Signaling: Per Time-Slot Enable....................106
Common Channel Signaling..............................................................................107
Signaling Access ...............................................................................................107
Signaling Processing Options ...........................................................................108
10.5.1 Signaling Freeze ..................................................................................108
10.5.2 Signaling Debounce .............................................................................108
10.3
10.4
10.5
Datasheet
Document Number: 278594
Revision Number: 003
Revision Date: December 2, 2003
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