USBLC6-4
Very low capacitance ESD protection
Datasheet
-
production data
•
Low leakage current for longer operation of
battery powered devices
•
Fast response time
•
Consistent D+ / D- signal balance:
– Best capacitance matching tolerance
I/O to GND = 0.015 pF
– Compliant with USB 2.0 requirements
< 1 pF
SOT23-6L
Figure 1. Functional diagram
I/O1
1
1
6
Complies with the following standards
•
IEC 61000-4-2 level 4:
– 15 kV (air discharge)
– 8 kV (contact discharge)
I/O4
GND
2
5
V
BUS
I/O2
3
4
I/O3
Applications
•
USB 2.0 ports up to 480 Mb/s (high speed)
•
Backwards compatible with USB 1.1 low and
full speed
•
Ethernet port: 10/100 Mb/s
•
SIM card protection
•
Video line protection
•
Portable electronics
Features
•
4 data-line protection
•
Protects V
BUS
•
Very low capacitance: 3 pF typ.
•
Peak pulse power (8/20 µs): 130 W typ.
•
SOT23-6L package
•
RoHS compliant
Description
The USBLC6-4 is a monolithic application specific
device dedicated to ESD protection of high speed
interfaces, such as USB 2.0, Ethernet links and
video lines.
Its very low line capacitance secures a high level
of signal integrity without compromising in
protecting sensitive chips against the most
stringent characterized ESD strikes.
Benefits
•
Very low capacitance between lines to GND for
optimized data integrity and speed
•
Low PCB space consumption, 9 mm²
maximum foot print
•
Enhanced ESD protection: IEC 61000-4-2
level 4 compliance guaranteed at device level,
hence greater immunity at system level
•
ESD protection of V
BUS
: allows ESD current
flowing to ground when ESD event occurs on
data line
•
High reliability offered by monolithic integration
November 2015
This is information on a product in full production.
DocID11068 Rev 7
1/13
www.st.com
Characteristics
USBLC6-4
1
Characteristics
Table 1. Absolute ratings
Symbol
Parameter
IEC 61000-4-2 air discharge
IEC 61000-4-2 contact discharge
MIL STD883C-Method 3015-6
Value
15
15
25
-55 to +150
-40 to +125
260
Unit
V
PP
T
stg
T
j
T
L
Peak pulse voltage
Storage temperature range
kV
°C
°C
°C
Operating junction temperature range
Lead solder temperature (10 seconds duration)
Table 2. Electrical characteristics (T
amb
= 25 °C)
Value
Symbol
I
RM
V
BR
V
F
Parameter
Leakage current
Breakdown voltage
between V
BUS
and GND
Forward voltage
Test Conditions
Min.
V
RM
= 5.25 V
I
R
= 1 mA
I
F
= 10 mA
I
PP
= 1 A, 8/20 µs
Any I/O pin to GND
V
CL
Clamping voltage
I
PP
= 5 A, 8/20 µs
Any I/O pin to GND
Capacitance between I/O
V
R
= 1.65 V
and GND
3
0.015
Capacitance between I/O V
R
= 1.65 V
1.85
0.04
2.7
pF
17
4
pF
V
6
Typ.
10
Max.
150
10
0.86
12
nA
V
V
V
Unit
C
i/o-GND
ΔC
i/o-GND
C
i/o-i/o
ΔC
i/o-i/o
2/13
DocID11068 Rev 7
USBLC6-4
Characteristics
Figure 2. Capacitance versus voltage
(typical values)
C(pF)
5.0
4.5
4.0
3.5
C
O
=I/O-GND
F=1MHz
V
OSC
=30mV
RMS
T
j
=25°C
Figure 3. Line capacitance versus frequency
(typical values)
C(pF)
5.0
4.5
V
CC
=0V
V
OSC
=30mV
RMS
T
j
=25°C
4.0
3.5
V
CC
=1.65V
3.0
2.5
C
j
=I/O-I/O
3.0
2.5
2.0
1.5
1.0
2.0
1.5
1.0
0.5
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Data line voltage (V)
0.5
0.0
1
10
F(MHz)
100
1000
Figure 4. Relative variation of leakage current
versus junction temperature (typical values)
I
RM
[T
j
] / I
RM
[T
j
=25°C]
100
V
BUS
=5V
Figure 5. Frequency response
S21(dB)
0.00
-5.00
10
-10.00
-15.00
T
j
(°C)
1
25
50
75
100
125
F(Hz)
-20.00
100.0k
1.0M
10.0M
100.0M
1.0G
DocID11068 Rev 7
3/13
13
Technical information
USBLC6-4
2
2.1
Technical information
Surge protection
The USBLC6-4SC6 is particularly optimized to provide surge protection based on the rail to
rail topology.
The clamping voltage V
CL
can be calculated as follows:
V
CL
+ = V
TRANSIL
+ V
F
for positive surges
V
CL
- = - V
F
for negative surges
with: V
F
= V
T
+ R
d
.I
p
(V
F
forward drop voltage, V
T
forward drop threshold voltage
Calculation example
We assume that the value of the dynamic resistance of the clamping diode is typically:
R
d
= 0.5
Ω
and V
T
= 1.1 V.
For an IEC 61000-4-2 surge level 4 (Contact Discharge: V
g
= 8 kV, R
g
= 330
Ω),
V
BUS
= +5 V, and if in a first approximation, we assume that:
I
p
= V
g
/ R
g
= 24 A.
So, we find:
V
CL
+ = +31.2 V
V
CL
- = -13.1 V
Note:
The calculations do not take into account phenomena due to parasitic inductances.
2.2
Surge protection application example
If we consider that the connections from the pin V
BUS
to V
CC
, from I/O to data line and from
GND to PCB GND plane are implemented as racks 10 mm long and 0.5 mm large, we can
assume that the parasitic inductances L
VBUS
L
I/0
and L
GND
of these tracks are about 6 nH.
So, when an IEC 61000-4-2 surge occurs, due to the rise time of this spike (t
r
= 1 ns), the
voltage V
CL
has an extra value equal to L
I/0
·dI/dt, + L
GND
·dI/dt
The dI/dt is calculated as:
dI/dt = I
p
/t
r
= 24 A/ns
The overvoltage due to the parasitic inductances is:
L
I/0
·dI/dt, = L
GND
·dI/dt = 6 x 24 = 144 V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the
clamping voltage will be:
V
CL
+ = +31.2 + 144 + 144 = 319.2 V
V
CL
- = -13.1 - 144 -144 = -301.1 V
We can significantly reduce this phenomena with simple layout optimization. It is for this
reason that some recommendations have to be followed (see
2.3: How to ensure good ESD
protection).
4/13
DocID11068 Rev 7
USBLC6-4
Technical information
Figure 6. ESD behavior: parasitic phenomena due to unsuitable layout
ESD sur ge on data line
V
BUS
Data line
L
I/O
L
I/O
di
dt
L
VBUS
V
CC
pin
V
F
V
TRANSIL
I/O pin
V
CL
V
TRANSIL
+ V
F
t
t
r
= 1 ns
GND pin
t
r
= 1 ns
L
GND
L
GND
di
dt
- V
F
t
L
I/O
di + L
GND
di
dt
dt
V
CL+
Positive
Sur ge
V
CL
+ = V
TRANSIL
+ V
F
+ L
I/O
di + L
GND
di
dt
dt
V
CL-
= -V
F
- L
I/O
di - L
GND
di
dt
dt
V TRANSIL = VBR + Rd.Ip
sur ge > 0
sur ge > 0
-L
I/O
di - L
GND
di
dt
dt
Negative
Sur ge
V
CL-
2.3
How to ensure good ESD protection
While the USBLC6-4SC6 provides high immunity to ESD surge, efficient protection depends
on the layout of the board. In the same way, with the rail to rail topology, the track from data
lines to I/O pins, from V
CC
to the V
BUS
pin and from GND plane to GND pin must be as short
as possible to avoid overvoltages due to parasitic phenomena (see
Figure 7
and
Figure 8
for layout considerations)
Figure 7. ESD behavior: optimized layout and
addition of a capacitance of 100 nF
Figure 8. ESD behavior: measurement
conditions (with coupling capacitance)
ESD SURGE
TEST BOARD
Unsuitable layout
IN
OUT
USBLC6-4SC6
Vbus
Optimized layout
DocID11068 Rev 7
5/13
13
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