®
X5168, X5169
(Replaces X25268, X25169)
Data Sheet
June 15, 2006
FN8130.2
CPU Supervisor with 16Kbit SPI EEPROM
These devices combine three popular functions, Power-on
Reset Control, Supply Voltage Supervision, and Block Lock
Protect Serial EEPROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
The device’s low V
CC
detection circuitry protects the user’s
system from low voltage conditions by holding
RESET/RESET active when V
CC
falls below a minimum V
CC
trip point. RESET/RESET remains asserted until V
CC
returns
to proper operating level and stabilizes. Five industry
standard V
TRIP
thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed to
meet custom requirements or to fine-tune the threshold in
applications requiring higher precision.
Features
• Low V
CC
Detection and Reset Assertion
- Five standard reset threshold voltages
- Re-program low V
CC
reset threshold voltage using
special programming sequence
- Reset signal valid to V
CC
= 1V
• Long Battery Life with Low Power Consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
• 16Kbits of EEPROM
• Built-in Inadvertent Write Protection
- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block
Lock
™
protection
- In circuit programmable ROM mode
• 2MHz SPI Interface Modes (0,0 & 1,1)
• Minimize EEPROM Programming Time
- 32-byte page write mode
- Self-timed write cycle
- 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V Power Supply
Operation
• Available Packages
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Block Diagram
WP
SI
SO
SCK
CS
Data
Register
Command
Decode &
Control
Logic
Protect Logic
Status
Register
4Kbits
4Kbits
8Kbits
EEPROM Array
Reset
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET/RESET
V
CC
V
TRIP
+
-
X5168 = RESET
X5169 = RESET
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5168, X5169
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
X5168P-4.5A
X5168PZ-4.5A
(Note)
X5168PI-4.5A
X5168PIZ-4.5A
(Note)
X5168S8-4.5A
X5168S8Z-4.5A
(Note)
X5168S8I-4.5A*
PART
MARKING
X5168P AL
PART NUMBER
RESET
(ACTIVE HIGH)
X5169P-4.5A
PART
MARKING
X5169P AL
X5169P Z AL
X5169P AM
X5169P Z AM
X5169 AL
X5169 Z AL
X5169 AM
X5169 Z AM
X5169V AL
V
CC
RANGE V
TRIP
RANGE
(V)
(V)
4.5-5.5
4.5-4.75
TEMP
RANGE (°C)
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
4.5-5.5
4.25-4.5
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
2.7-5.5
2.85-3.0
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
8 Ld PDIP
8 Ld PDIP**
(Pb-free)
8 Ld PDIP
8 Ld PDIP**
(Pb-free)
8 Ld SOIC
8 Ld SOIC
(Pb-free)
8 Ld SOIC
8 Ld SOIC
(Pb-free)
PKG.
DWG #
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
X5168P Z AL X5169PZ-4.5A
(Note)
X5168P AM
X5169PI-4.5A
X5168P Z AM X5169PIZ-4.5A
(Note)
X5168 AL
X5168 Z AL
X5168 AM
X5169S8-4.5A
X5169S8Z-4.5A
(Note)
X5169S8I-4.5A
X5169S8IZ-4.5A
(Note)
X5169V14-4.5A
X5168S8IZ-4.5A* X5168 Z AM
(Note)
X5168V14-4.5A
X5168V AL
14 Ld TSSOP M14.173
14 Ld TSSOP M14.173
(Pb-free)
14 Ld TSSOP M14.173
14 Ld TSSOP M14.173
(Pb-free)
8 Ld PDIP
8 Ld PDIP**
(Pb-free)
8 Ld PDIP
8 Ld PDIP**
(Pb-free)
8 Ld SOIC
8 Ld SOIC
(Pb-free)
8 Ld SOIC
8 Ld SOIC
(Pb-free)
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
X5168V14Z-4.5A X5168V Z AL X5169V14Z-4.5A X5169V Z AL
(Note)
(Note)
X5168V14I-4.5A
X5168V AM
X5169V14I-4.5A
X5169V AM
X5168V14IZ-4.5A X5168V Z AM X5169V14IZ-4.5A X5169V Z AM
(Note)
(Note)
X5168P
X5168PZ (Note)
X5168PI
X5168P
X5168P Z
X5168P I
X5169P
X5169PZ (Note)
X5169PI
X5169P
X5169P Z
X5169P I
X5168PIZ (Note) X5168P Z I
X5168S8*
X5168S8Z*
(Note)
X5168S8I*
X5168S8IZ*
(Note)
X5168V14*
X5168V14Z*
(Note)
X5168V14I*
X5168V14IZ*
(Note)
X5168P-2.7A
X5168PZ-2.7A
(Note)
X5168PI-2.7A
X5168PIZ-2.7A
(Note)
X5168S8-2.7A*
X5168
X5168 Z
X5168 I
X5168 Z I
X5168V
X5168V Z
X5168V I
X5168V Z I
X5168P AN
X5169PIZ (Note) X5169P Z I
X5169S8*
X5169S8Z*
(Note)
X5169S8I*
X5169S8IZ*
(Note)
X5169V14*
X5169V14Z*
(Note)
X5169V14I*
X5169V14IZ*
(Note)
X5169P-2.7A
X5169
X5169 Z
X5169 I
X5169 Z I
X5169V
X5169V Z
X5169V I
X5169V Z I
X5169P AN
X5169P Z AN
X5169P AP
X5169P Z AP
X5169 AN
X5169 Z AN
X5169 AP
X5169 Z AP
14 Ld TSSOP M14.173
14 Ld TSSOP M14.173
(Pb-free)
14 Ld TSSOP M14.173
14 Ld TSSOP M14.173
(Pb-free)
8 Ld PDIP
8 Ld PDIP**
(Pb-free)
8 Ld PDIP
8 Ld PDIP**
(Pb-free)
8 Ld SOIC
8 Ld SOIC
(Pb-free)
8 Ld SOIC
8 Ld SOIC
(Pb-free)
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
X5168P Z AN X5169PZ-2.7A
(Note)
X5168P AP
X5169PI-2.7A
X5168P Z AP X5169PIZ-2.7A
(Note)
X5168 AN
X5169S8-2.7A
X5169S8Z-2.7A
(Note)
X5169S8I-2.7A
X5169S8IZ-2.7A
(Note)
X5168S8Z-2.7A* X5168 Z AN
(Note)
X5168S8I-2.7A*
X5168S8IZ-2.7A
(Note)
X5168 AP
X5168 Z AP
2
FN8130.2
June 15, 2006
X5168, X5169
Ordering Information
(Continued)
PART NUMBER
RESET
(ACTIVE LOW)
X5168V14-2.7A
PART
MARKING
X5168V AN
PART NUMBER
RESET
(ACTIVE HIGH)
X5169V14-2.7A
PART
MARKING
X5168V AN
V
CC
RANGE V
TRIP
RANGE
(V)
(V)
2.7-5.5
2.85-3.0
TEMP
RANGE (°C)
0 to 70
0 to 70
-40 to 85
-40 to 85
2.7-5.5
2.55-2.7
0 to 70
PACKAGE
PKG.
DWG #
14 Ld TSSOP M14.173
14 Ld TSSOP M14.173
(Pb-free)
14 Ld TSSOP M14.173
14 Ld TSSOP M14.173
(Pb-free)
8 Ld PDIP
8 Ld PDIP**
(Pb-free)
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
X5168V14Z-2.7A X5168V Z AN X5169V14Z-2.7A X5169V Z AN
(Note)
(Note)
X5168V14I-2.7A
X5168V AP
X5169V14I-2.7A
X5169V AP
X5168V14IZ-2.7A X5168V Z AP X5169V14IZ-2.7A X5169V Z AP
(Note)
(Note)
X5168P-2.7
X5168PZ-2.7
(Note)
X5168PI-2.7
X5168PIZ-2.7
(Note)
X5168S8-2.7*
X5168S8Z-2.7*
(Note)
X5168S8I-2.7*
X5168S8IZ-2.7*
(Note)
X5168V14-2.7*
X5168V14Z-2.7*
(Note)
X5168V14I-2.7*
X5168P F
X5168P Z F
X5168P G
X5168P Z G
X5168 F
X5168 Z F
X5168 G
X5168 Z G
X5168V F
X5168V Z F
X5168V G
X5169P-2.7
X5169PZ-2.7
(Note)
X5169PI-2.7
X5169PIZ-2.7
(Note)
X5169S8-2.7*
X5169S8Z-2.7*
(Note)
X5169S8I-2.7*
X5169S8IZ-2.7*
(Note)
X5169V14-2.7*
X5169V14Z-2.7*
(Note)
X5169V14I-2.7*
X5169P F
X5169P Z F
X5169P G
X5169P Z G
X5169 F
X5169 Z F
X5169 G
X5169 Z G
X5169V F
X5169V Z F
X5168V G
-40 to 85
8 Ld PDIP
8 Ld PDIP**
(Pb-free)
0 to 70
8 Ld SOIC
8 Ld SOIC
(Pb-free)
-40 to 85
8 Ld SOIC
8 Ld SOIC
(Pb-free)
0 to 70
0 to 70
-40 to 85
-40 to 85
14 Ld TSSOP M14.173
14 Ld TSSOP M14.173
(Pb-free)
14 Ld TSSOP M14.173
14 Ld TSSOP M14.173
(Pb-free)
X5168V14IZ-2.7* X5168V Z G
(Note)
X5169V14IZ-2.7* X5168V Z G
(Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add "-T1" suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Pin Configuration
14 LD TSSOP
8 LD SOIC/PDIP
CS
SO
WP
V
SS
1
2
3
4
X5168/X5169 8
7
6
5
V
CC
RESET/RESET
SCK
SI
CS
SO
NC
NC
NC
WP
V
SS
1
2
3
4
5
6
7
X5168/X5169
14
13
12
11
10
9
8
V
CC
RESET/RESET
NC
NC
NC
SCK
SI
3
FN8130.2
June 15, 2006
X5168, X5169
Pin Description
PIN
(SOIC/PDIP)
1
PIN TSSOP
1
NAME
CS
FUNCTION
Chip Select Input.
CS HIGH, deselects the device and the SO output
pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be
in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior
to the start of any operation after power-up, a HIGH to LOW transition on CS is required.
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
Serial Clock.
The serial clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
Write Protect.
The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the watchdog timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output.
RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever V
CC
falls below the minimum V
CC
sense level. It will remain active until V
CC
rises above
the minimum V
CC
sense level for 200ms. RESET/RESET goes active if the watchdog timer is
enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-
up at about 1V and remains active for 200ms after the power supply stabilizes.
No internal connections
2
5
2
8
SO
SI
6
9
SCK
3
4
8
7
6
7
14
13
WP
V
SS
V
CC
RESET/
RESET
3-5,10-12
NC
4
FN8130.2
June 15, 2006
X5168, X5169
Principles of Operation
Power-on Reset
Application of power to the X5168, X5169 activates a power-
on reset circuit. This circuit goes active at about 1V and pulls
the RESET/RESET pin active. This signal prevents the
system microprocessor from starting to operate with
insufficient voltage or prior to stabilization of the oscillator.
When V
CC
exceeds the device V
TRIP
value for 200ms
(nominal) the circuit releases RESET/RESET, allowing the
processor to begin executing code.
Resetting the V
TRIP
Voltage
This procedure sets the V
TRIP
to a “native” voltage level. For
example, if the current V
TRIP
is 4.4V and the V
TRIP
is reset,
the new V
TRIP
is something less than 1.7V. This procedure
must be used to set the voltage to a lower value.
To reset the V
TRIP
voltage, apply a voltage between 2.7 and
5.5V to the V
CC
pin. Tie the CS pin, the WP pin, and the SCK
pin HIGH. RESET/RESET and SO pins are left unconnected.
Then apply the programming voltage V
P
to the SI pin ONLY
and pulse CS LOW then HIGH. Remove V
P
and the
sequence is complete.
Low Voltage Monitoring
During operation, the X5168, X5169 monitors the V
CC
level
and asserts RESET/RESET if supply voltage falls below a
preset minimum V
TRIP
. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until V
CC
returns and exceeds V
TRIP
for 200ms.
CS
SCK
V
CC
V
P
SI
FIGURE 2. RESET V
TRIP
VOLTAGE
V
CC
Threshold Reset Procedure
The X5168, X5169 has a standard V
CC
threshold (V
TRIP
)
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard V
TRIP
is not exactly right, or for higher precision in
the V
TRIP
value, the X5168, X5169 threshold may be
adjusted.
Setting the V
TRIP
Voltage
This procedure sets the V
TRIP
to a higher voltage value. For
example, if the current V
TRIP
is 4.4V and the new V
TRIP
is
4.6V, this procedure directly makes the change. If the new
setting is lower than the current setting, then it is necessary
to reset the trip point before setting the new value.
To set the new V
TRIP
voltage, apply the desired V
TRIP
threshold to the V
CC
pin and tie the CS pin and the WP pin
HIGH. RESET/RESET and SO pins are left unconnected.
Then apply the programming voltage V
P
to both SCK and SI
and pulse CS LOW then HIGH. Remove V
P
and the
sequence is complete.
CS
V
P
SCK
V
P
SI
FIGURE 1. SET V
TRIP
VOLTAGE
5
FN8130.2
June 15, 2006
Test/Measurement
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