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ICS91718YGLF-T

Description
PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), PDSO8, 4.40 MM, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-8
Categorylogic    logic   
File Size81KB,11 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

ICS91718YGLF-T Overview

PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), PDSO8, 4.40 MM, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-8

ICS91718YGLF-T Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts8
Reach Compliance Codecompliant
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G8
JESD-609 codee3
length4.4 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals8
Actual output times2
Maximum operating temperature85 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelOTHER
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3 mm
minfmax80 MHz
Base Number Matches1
Integrated
Circuit
Systems, Inc.
ICS91718
Low EMI, Spread Modulating, Clock Generator
Features:
ICS91718 is a Spread Spectrum Clock targeted
for Mobile PC and LCD panel applications.
Generates an EMI optimized clock signal (EMI
peak reduction of 7-14 dB on 3rd-19th harmonics)
through use of Spread Spectrum techniques.
ICS91718 operates with input frequencies at
14.318 - 80 MHz.
Spread modulation frequency range is 20kHz to
40kHz.
Spread percentage/type programming through
I
2
C.
Specifications:
Supply Voltages: V
DD
= 3.3V ±0.3V
Cyc to Cyc jitter: <150ps
Output duty cycle 45/55%
Guarantees +85°C operational condition
8-pin SOIC (150 mil) package
Pin Configuration
CLKIN
VDD
GND
**
CLKOUT/FS_IN0
1
2
3
4
8
7
6
5
PD#
*
SCLK
SDATA
REF_OUT/FS_IN1
**
8-pin SOIC & TSSOP
Notes:
* Internal pull-up resistor
** Internal pull-down resistor
Input Select Functionality
FS_IN1 FS_IN0
0
0
1
1
0
1
0
1
MHz
14.318 in
48.00 out
14.318 in
66.66 out
48.00 in/out
66.66 in/out
48.00 in/out
66.66 in/out
SPREAD %
-1.0% down sprd
-1.0% down sprd
-1.0% down sprd
+/-1.0% center sprd
Block Diagram
REFOUT
CLKIN
PLL1
Spread
Spectrum
Spectrum
CLKOUT
CLKOUT
PD#
FS_IN0:1
SDATA
SD
SCLK
Control
Logic
Config.
Reg.
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