MX29LV161D T/B
MX29LV161D T/B
DATASHEET
P/N:PM1359
REV. 1.0, JUN. 03, 2010
1
MX29LV161D T/B
Contents
FEATURES ............................................................................................................................................................ 5
GENERAL DESCRIPTION .................................................................................................................................... 6
PIN CONFIGURATIONS ........................................................................................................................................ 7
PIN DESCRIPTION ................................................................................................................................................ 9
BLOCK DIAGRAM............................................................................................................................................... 10
BLOCK DIAGRAM DESCRIPTION ..................................................................................................................... 11
BLOCK STRUCTURE.......................................................................................................................................... 12
Table 1-1. MX29LV161DT SECTOR ARCHITECTURE ............................................................................. 12
Table 1-2. MX29LV161DB SECTOR ARCHITECTURE ............................................................................ 13
BUS OPERATIONS ............................................................................................................................................. 14
Table 2-1. BUS OPERATION ..................................................................................................................... 14
Table 2-2. BUS OPERATION ..................................................................................................................... 15
FUNCTIONAL OPERATION DESCRIPTIONS .................................................................................................... 16
WRITE COMMANDS/COMMAND SEQUENCES ...................................................................................... 16
REQUIREMENTS FOR READING ARRAY DATA...................................................................................... 16
RESET# OPERATION ............................................................................................................................... 17
SECTOR PROTECT OPERATION ............................................................................................................ 17
CHIP UNPROTECT OPERATION............................................................................................................. 17
HARDWARE WRITE PROTECT ................................................................................................................ 17
ACCELERATED PROGRAMMING OPERATION ..................................................................................... 17
TEMPORARY SECTOR UNPROTECT OPERATION ............................................................................... 18
AUTOMATIC SELECT OPERATION.......................................................................................................... 18
VERIFY SECTOR PROTECT STATUS OPERATION ................................................................................ 18
DATA PROTECTION .................................................................................................................................. 18
LOW VCC WRITE INHIBIT ........................................................................................................................ 18
WRITE PULSE "GLITCH" PROTECTION.................................................................................................. 19
LOGICAL INHIBIT ...................................................................................................................................... 19
POWER-UP SEQUENCE .......................................................................................................................... 19
POWER-UP WRITE INHIBIT ..................................................................................................................... 19
POWER SUPPLY DECOUPLING .............................................................................................................. 19
COMMAND OPERATIONS .................................................................................................................................. 20
TABLE 3. MX29LV161D T/B COMMAND DEFINITIONS ........................................................................... 20
AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY ..................................................................... 21
ERASING THE MEMORY ARRAY ............................................................................................................. 21
SECTOR ERASE ....................................................................................................................................... 22
CHIP ERASE............................................................................................................................................. 23
SECTOR ERASE SUSPEND ..................................................................................................................... 23
SECTOR ERASE RESUME ....................................................................................................................... 24
AUTOMATIC SELECT OPERATIONS ....................................................................................................... 24
AUTOMATIC SELECT COMMAND SEQUENCE ...................................................................................... 24
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REV. 1.0, JUN. 03, 2010
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MX29LV161D T/B
READ MANUFACTURER ID OR DEVICE ID ............................................................................................ 25
VERIFY SECTOR PROTECTION .............................................................................................................. 25
RESET ...................................................................................................................................................... 25
COMMON FLASH MEMORY INTERFACE (CFI) MODE .................................................................................... 26
QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE .................................................. 26
Table 4-1. CFI mode: Identification Data Values
........................................................................................ 26
Table 4-2. CFI Mode: System Interface Data Values
................................................................................. 26
Table 4-3. CFI Mode: Device Geometry Data Values
................................................................................. 27
Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
........................................... 28
ELECTRICAL CHARACTERISTICS ................................................................................................................... 29
ABSOLUTE MAXIMUM STRESS RATINGS.............................................................................................. 29
OPERATING TEMPERATURE AND VOLTAGE ......................................................................................... 29
DC CHARACTERISTICS ........................................................................................................................... 30
SWITCHING TEST CIRCUIT ..................................................................................................................... 31
SWITCHING TEST WAVEFORM .............................................................................................................. 31
AC CHARACTERISTICS ........................................................................................................................... 32
WRITE COMMAND OPERATION........................................................................................................................ 33
Figure 1. COMMAND WRITE OPERATION
............................................................................................... 33
READ/RESET OPERATION ................................................................................................................................ 34
Figure 2. READ TIMING WAVEFORM
....................................................................................................... 34
Figure 3. RESET# TIMING WAVEFORM
.................................................................................................. 35
ERASE/PROGRAM OPERATION ....................................................................................................................... 36
Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM
..................................................................... 36
Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
........................................................... 37
Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
............................................................... 38
Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
................................................... 39
Figure 8. ERASE SUSPEND/RESUME FLOWCHART
............................................................................. 40
Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORM
......................................................................... 41
Figure 10. ACCELERATED PROGRAM TIMING DIAGRAM
.................................................................... 41
Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM
.................................................................. 42
Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
................................................... 43
SECTOR PROTECT/CHIP UNPROTECT ........................................................................................................... 44
Figure 13. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control)
........................... 44
Figure 14. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv
........................................................... 45
Figure 15. CHIP UNPROTECT ALGORITHM WITH RESET#=Vhv
........................................................... 46
Table 5. TEMPORARY SECTOR UNPROTECT ........................................................................................ 47
Figure 16. TEMPORARY SECTOR UNPROTECT WAVEFORM
.............................................................. 47
Figure 17. TEMPORARY SECTOR UNPROTECT FLOWCHART
............................................................. 48
Figure 18. SILICON ID READ TIMING WAVEFORM
................................................................................. 49
WRITE OPERATION STATUS ............................................................................................................................. 50
Figure 19. DATA# POLLING TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM)
...................... 50
Figure 20. DATA# POLLING ALGORITHM
................................................................................................ 51
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REV. 1.0, JUN. 03, 2010
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MX29LV161D T/B
Figure 21. TOGGLE BIT TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM)
........................... 52
Figure 22. TOGGLE BIT ALGORITHM.......................................................................................................
53
RECOMMENDED OPERATING CONDITIONS ................................................................................................... 54
ERASE AND PROGRAMMING PERFORMANCE .............................................................................................. 55
DATA RETENTION .............................................................................................................................................. 55
LATCH-UP CHARACTERISTICS ........................................................................................................................ 55
TSOP PIN CAPACITANCE .................................................................................................................................. 55
ORDERING INFORMATION ................................................................................................................................ 56
PART NAME DESCRIPTION ............................................................................................................................... 57
PACKAGE INFORMATION .................................................................................................................................. 58
REVISION HISTORY ........................................................................................................................................... 62
P/N:PM1359
REV. 1.0, JUN. 03, 2010
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MX29LV161D T/B
16M-BIT [1M x 16] 3V SUPPLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• Word mode only
- 1,048,576 x 16
• Sector Structure
- 8K-Word x 1, 4K-Word x 2, 16K-Word x 1, 32K-Word x 31
- Provides sector protect function to prevent program or erase operation in the protected sector
- Provides chip unprotect function to allow code changing
- Provides temporary sector unprotect function for code changing in previously protected sector
• Power Supply Operation
- VCC 2.7 to 3.6 volt for read, erase, and program operations
- VI/O 1.65V to 3.6V for Input/Output
• Latch-up protected to 100mA from -1V to 1.5xVcc
• Low Vcc write inhibit : Vcc ≤ Vlko
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
PERFORMANCE
• High Performance
- Fast access time: 90ns
- Word program time: 11us/word (typical)
- Fast erase time: 0.7s/sector, 15s/chip (typical)
• Low Power Consumption
- Low active read current: 5mA (typical) at 5MHz
- Low standby current: 5uA (typical)
• 100,000 erase/program cycle (typical)
• 20 years data retention
SOFTWARE FEATURES
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being
erased
• Status Reply
- Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
• WP#/ACC
- Provide accelerated program capability
PACKAGE
• 48-Pin TSOP
• 48-Ball CSP (TFBGA)
• 48-Ball WFBGA/XFLGA
•
All Pb-free devices are RoHS Compliant
P/N:PM1359
REV. 1.0, JUN. 03, 2010
5