IDT5V9888
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
3.3V EEPROM
PROGRAMMABLE CLOCK
GENERATOR
FEATURES:
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Three internal PLLs
Internal non-volatile EEPROM
JTAG and FAST mode I
2
C serial interfaces
Input Frequency Ranges: 1MHz to 400MHz
Output Frequency Ranges:
−
LVTTL: up to 200MHz
−
LVPECL/ LVDS: up to 500MHz
Reference Crystal Input with programmable oscillator gain and
programmable linear load capacitance
−
Crystal Frequency Range: 8MHz to 50MHz
Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
10-bit post-divider blocks
Fractional Dividers
Two of the PLLs support Spread Spectrum Generation
capability
I/O Standards:
−
Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
−
Inputs - 3.3V LVTTL/ LVCMOS
Programmable Slew Rate Control
Programmable Loop Bandwidth Settings
Programmable output inversion to reduce bimodal jitter
Redundant clock inputs with glitchless auto and manual
switchover options
JTAG Boundary Scan
Individual output enable/disable
Power-down mode
3.3V V
DD
Available in TQFP and VFQFPN packages
IDT5V9888
The IDT5V9888 is a programmable clock generator intended for high
performance data-communications, telecommunications, consumer, and
networking applications. There are three internal PLLs, each individually
programmable, allowing for three unique non-integer-related frequencies.
The frequencies are generated from a single reference clock. The
reference clock can come from one of the two redundant clock inputs. A
glitchless automatic or manual switchover function allows any one of the
redundant clocks to be selected during normal operation.
The IDT5V9888 can be programmed through the use of the I
2
C or JTAG
interfaces. The programming interface enables the device to be pro-
grammed when it is in normal operation or what is commonly known as in-
system programmable. An internal EEPROM allows the user to save and
restore the configuration of the device without having to reprogram it on
power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback
divider. This allows the user to generate three unique non-integer-related
frequencies. The PLL loop bandwidth is programmable to allow the user
to tailor the PLL response to the application. For instance, the user can tune
the PLL parameters to minimize jitter generation or to maximize jitter
attenuation. Spread spectrum generation and fractional divides are
allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the
six output banks are configurable to be LVTTL, LVPECL, or LVDS. The
other four output banks are LVTTL. The outputs are connected to the PLLs
via the switch matrix. The switch matrix allows the user to route the PLL
outputs to any output bank. This feature can be used to simplify and optimize
the board layout. In addition, each output's slew rate and enable/disable
function can be programmed.
DESCRIPTION:
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
c
2007
Integrated Device Technology, Inc.
OCTOBER 2007
1
DSC 7044/13
IDT5V9888
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name
CLKIN
XTALIN/REFIN
XTALOUT
GIN0/SDAT/TDI
GIN1/SCLK/TCK
GIN2/TMS
WRITE ENABLE
GIN3/TRST
GIN4/CLK_SEL
SHUTDOWN/OE
I
2
C/JTAG
OUT1
OUT2
OUT3
OUT4
OUT4
OUT5
OUT5
OUT6
GOUT0/TDO/LOSS_LOCK
GOUT1/LOSS_CLKIN
V
DD
GND
PF32
Pin#
1
4
5
19
20
24
27
25
21
28
22
6
29
8
10
11
15
16
13
31
3
7,12,17,
23,26,32
2,9,14,
18,30
NL28
Pin#
1
4
5
16
17
21
24
22
18
23
19
6
25
7
8
9
13
14
11
27
3
10,15,20
28
2,12,26
I/O
I
I
O
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
Type
LVTTL
LVTTL
LVTTL
LVTTL
(3)
LVTTL
(3)
LVTTL
(3)
LVTTL
(3)
LVTTL
(3)
LVTTL
(3)
LVTTL
(3)
3-level
(2)
LVTTL
LVTTL
LVTTL
Adjustable
Adjustable
(1)
(1)
Description
Input Clock
CRYSTAL_IN - Reference crystal input or external reference clock input
CRYSTAL_OUT -Reference crystal feedback
Multi-purpose inputs. Can be used for Frequency Control, SDAT(I
2
C), or TDI(JTAG).
Multi-Purpose inputs. Can be used for Frequency Control, SCLK(I
2
C), or TCK(JTAG).
Multi-Purpose inputs. Can be used for Frequency Control or TMS (JTAG).
Write Enable pin. This pin must be pulled HIGH during normal operation. HIGH =
normal operation, LOW = Enable writing to internal EEPROM.
Multi-Purpose inputs. Can be used for Frequency Control or
TRST
(JTAG).
Multi-Purpose inputs. Can be used for Frequency Control or input clock selector.
Enables/disables the outputs or powers down the chip. The SP bit (0x1C) controls the
polarity of the signal to be either active HIGH or LOW. (Default is active HIGH.)
I
2
C (HIGH) or MFC Mode (MID) or JTAG Programming (LOW).
Configurable clock output 1. Can also be used to buffer the reference clock.
Configurable clock output 2
Configurable clock output 3
Configurable clock output 4, Single-Ended or Differential when combined with
OUT4
Configurable complementary clock output 4, Single-Ended or Differential when
combined with OUT4
Configurable clock output 5, Single-Ended or Differential when combined with
OUT5
Configurable complementary clock output 5, Single-Ended or Differential when
combined with OUT5
Configurable clock output 6
Multi-Purpose Output. Can be programmed to use as PLL LOCK signal, LOSS_LOCK
or TDO in JTAG mode.
Multi-Purpose Output. Can be programmed to use as LOSS_CLKIN.
3.3V Power Supply
Ground
Adjustable
(1)
Adjustable
(1)
LVTTL
LVTTL
(3)
LVTTL
NOTES:
1. Outputs are user programmable to drive single-ended 3.3V LVTTL, differential LVDS, or differential LVPECL interface levels.
2. 3-level inputs are static inputs and must be tied to V
DD
or GND or left floating. These inputs are internally biased to V
DD
/2. They are not hot-insertable or over voltage tolerant.
3. The JTAG (TDO, TMS, TCLK,
TRST,
and TDI) and I
2
C (SCLK and SDAT) signals share the same pins with GIN signals.
4
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