74AC08_08 datasheet, PDF - EEWORLD Datasheet

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74AC08_08: DescriptionAC SERIES, QUAD 2-INPUT AND GATE, PDSO14; Categorysemiconductor logic; File Size301KB，10 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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74AC08_08 Overview

AC SERIES, QUAD 2-INPUT AND GATE, PDSO14

74AC08_08 Parametric

Parameter Name	Attribute value
Number of functions	4
Number of terminals	14
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	6 V
Minimum supply/operating voltage	2 V
Rated supply voltage	3.3 V
Processing package description	0.150 INCH, MS-012, SOIC-14
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	RECTANGULAR
Package Size	SMALL OUTLINE
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	1.27 mm
terminal coating	MATTE TIN
Terminal location	DUAL
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
series	AC
Logic IC type	AND
Number of inputs	2
propagation delay TPD	10 ns

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74AC08, 74ACT08 — Quad 2-Input AND Gate

January 2008

74AC08, 74ACT08

Quad 2-Input AND Gate

Features

■

reduced by 50% on 74AC only

■

Outputs source/sink 24mA

General Description

The AC08/ACT08 contains four, 2-input AND gates.

Ordering Information

Order

Number

74AC08SC

74AC08SJ

74AC08MTC

74AC08PC

74ACT08SC

74ACT08MTC

74ACT08PC

Package

Number

M14A

M14D

MTC14

N14A

M14A

MTC14

N14A

Package Description

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Connection Diagram

Logic Symbol

IEEE/IEC

Pin Description

Pin Names

, B

Description

Inputs

Outputs

74AC08, 74ACT08 Rev. 1.5.1

www.fairchildsemi.com

74AC08_08 Related Products

	74AC08_08	74AC08	74ACT08	74ACT08PC	74ACT08SC	74AC08PC	74AC08SJ
Description	AC SERIES, QUAD 2-INPUT AND GATE, PDSO14	AC SERIES, QUAD 2-INPUT AND GATE, PDSO14	AC SERIES, QUAD 2-INPUT AND GATE, PDSO14	AC SERIES, QUAD 2-INPUT AND GATE, PDSO14	AC SERIES, QUAD 2-INPUT AND GATE, PDSO14	AC SERIES, QUAD 2-INPUT AND GATE, PDSO14	AC SERIES, QUAD 2-INPUT AND GATE, PDSO14
Number of functions	4	4	4	4	4	4	4
Number of terminals	14	14	14	14	14	14	14
Maximum operating temperature	85 Cel	85 Cel	85 Cel	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 Cel	-40 Cel	-40 Cel	-40 °C	-40 °C	-40 °C	-40 °C
surface mount	Yes	Yes	Yes	NO	YES	NO	YES
Terminal form	GULL WING	GULL WING	GULL WING	THROUGH-HOLE	GULL WING	THROUGH-HOLE	GULL WING
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
series	AC	AC	AC	ACT	ACT	AC	AC
Brand Name	-	-	-	Fairchild Semiconduc	Fairchild Semiconduc	Fairchild Semiconduc	Fairchild Semiconduc
Is it lead-free?	-	-	-	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	-	-	-	conform to	conform to	conform to	conform to
Maker	-	-	-	Fairchild	Fairchild	Fairchild	Fairchild
Parts packaging code	-	-	-	DIP	SOIC	DIP	SOP
package instruction	-	-	-	DIP, DIP14,.3	SOP, SOP14,.25	DIP, DIP14,.3	SOP, SOP14,.3
Contacts	-	-	-	14	14	14	14
Manufacturer packaging code	-	-	-	14LD, MDIP,JEDEC MS-001, .300\" WIDE	14LD,SOIC,JEDEC MS-012, .150\", NARROW BODY	14LD, MDIP,JEDEC MS-001, .300\" WIDE	14LD,SOP,EIAJ TYPE II, 5.3MM WIDE
Reach Compliance Code	-	-	-	unknow	compli	unknow	compli
ECCN code	-	-	-	EAR99	EAR99	EAR99	EAR99
JESD-30 code	-	-	-	R-PDIP-T14	R-PDSO-G14	R-PDIP-T14	R-PDSO-G14
JESD-609 code	-	-	-	e3	e3	e3	e3
length	-	-	-	19.18 mm	8.6235 mm	19.18 mm	10.2 mm
Load capacitance (CL)	-	-	-	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	-	-	-	AND GATE	AND GATE	AND GATE	AND GATE
MaximumI(ol)	-	-	-	0.024 A	0.024 A	0.012 A	0.012 A
Number of entries	-	-	-	2	2	2	2
Package body material	-	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	-	-	DIP	SOP	DIP	SOP
Encapsulate equivalent code	-	-	-	DIP14,.3	SOP14,.25	DIP14,.3	SOP14,.3
Package shape	-	-	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	-	-	-	IN-LINE	SMALL OUTLINE	IN-LINE	SMALL OUTLINE
method of packing	-	-	-	RAIL	RAIL	RAIL	RAIL
Peak Reflow Temperature (Celsius)	-	-	-	NOT APPLICABLE	NOT SPECIFIED	NOT APPLICABLE	260
power supply	-	-	-	5 V	5 V	3.3/5 V	3.3/5 V
Prop。Delay @ Nom-Su	-	-	-	10 ns	10 ns	10 ns	10 ns
propagation delay (tpd)	-	-	-	10 ns	10 ns	10 ns	10 ns
Certification status	-	-	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	-	-	-	NO	NO	NO	NO
Maximum seat height	-	-	-	5.08 mm	1.753 mm	5.08 mm	2.1 mm
Maximum supply voltage (Vsup)	-	-	-	5.5 V	5.5 V	6 V	6 V
Minimum supply voltage (Vsup)	-	-	-	4.5 V	4.5 V	2 V	2 V
Nominal supply voltage (Vsup)	-	-	-	5 V	5 V	3.3 V	3.3 V
technology	-	-	-	CMOS	CMOS	CMOS	CMOS
Terminal surface	-	-	-	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)
Terminal pitch	-	-	-	2.54 mm	1.27 mm	2.54 mm	1.27 mm
Maximum time at peak reflow temperature	-	-	-	NOT APPLICABLE	NOT SPECIFIED	NOT APPLICABLE	30
width	-	-	-	7.62 mm	3.9 mm	7.62 mm	5.3 mm
Base Number Matches	-	-	-	1	1	1	1

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