HD74ACT112RPEL datasheet, PDF - EEWORLD Datasheet

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HD74ACT112RPEL: DescriptionACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16; Categorylogic logic; File Size214KB，8 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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HD74ACT112RPEL Overview

ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16

HD74ACT112RPEL Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	SOIC
package instruction	SOP, SOP16,.25
Contacts	16
Reach Compliance Code	unknown
series	ACT
JESD-30 code	R-PDSO-G16
length	9.9 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	J-K FLIP-FLOP
Maximum Frequency@Nom-Sup	80000000 Hz
MaximumI(ol)	0.024 A
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	TAPE AND REEL
power supply	5 V
propagation delay (tpd)	14 ns
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Trigger type	NEGATIVE EDGE
width	3.95 mm
minfmax	80 MHz
Base Number Matches	1

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HD74AC112/HD74ACT112

Dual JK Negative Edge-Triggered Flip-Flop

REJ03D0244–0200Z

(Previous ADE-205-364 (Z))

Rev.2.00

Jul.16.2004

Description

The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flip-

flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs

may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum

setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse.

Features

•

Outputs Source/Sink 24 mA

•

HD74ACT112 has TTL-Compatible Inputs

•

Ordering Information: Ex. HD74AC112

Part Name

HD74AC112FPEL

HD74AC112RPEL

Package Type

SOP-16 pin (JEITA)

Package Code Package Abbreviation Taping Abbreviation (Quantity)

FP-16DAV

EL (2,000 pcs/reel)

EL (2,500 pcs/reel)

SOP-16 pin (JEDEC) FP-16DNV

Notes: 1. Please consult the sales office for the above package availability.

2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of

the package code.

Pin Arrangement

GND 8

(Top view)

16 V

12 K

11 J

9 Q

Rev.2.00, Jul.16.2004, page 1 of 7

HD74ACT112RPEL Related Products

	HD74ACT112RPEL	HD74AC112FP-EL	HD74AC112FPEL	HD74ACT112FP-EL	HD74ACT112FPEL	HD74ACT112RP-EL	HD74ACT112FPVEL	HD74AC112RP-EL	HD74ACT112RPVEL
Description	ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16	AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16	AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16	ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16	ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16	ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16	ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, LEAD FREE, SOP-16	AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16	ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, LEAD FREE, SOP-16
Parts packaging code	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC
package instruction	SOP, SOP16,.25	SOP,	SOP-16	SOP,	SOP-16	SOP,	SOP,	SOP,	SOP,
Contacts	16	16	16	16	16	16	16	16	16
Reach Compliance Code	unknown	unknown	compliant	unknown	compliant	unknown	unknown	unknown	compliant
series	ACT	AC	AC	ACT	ACT	ACT	ACT	AC	ACT
JESD-30 code	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
length	9.9 mm	10.06 mm	10.06 mm	10.06 mm	10.06 mm	9.9 mm	10.06 mm	9.9 mm	9.9 mm
Logic integrated circuit type	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP
Number of digits	2	2	2	2	2	2	2	2	2
Number of functions	2	2	2	2	2	2	2	2	2
Number of terminals	16	16	16	16	16	16	16	16	16
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	SOP	SOP	SOP	SOP	SOP	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
propagation delay (tpd)	14 ns	15 ns	15 ns	14 ns	14 ns	14 ns	14 ns	15 ns	14 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.75 mm	2.2 mm	2.2 mm	2.2 mm	2.2 mm	1.75 mm	2.2 mm	1.75 mm	1.75 mm
Maximum supply voltage (Vsup)	6 V	6 V	6 V	6 V	6 V	6 V	6 V	6 V	6 V
Minimum supply voltage (Vsup)	2 V	2 V	2 V	2 V	2 V	2 V	2 V	2 V	2 V
Nominal supply voltage (Vsup)	5 V	3.3 V	3.3 V	5 V	5 V	5 V	5 V	3.3 V	5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Trigger type	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE
width	3.95 mm	5.5 mm	5.5 mm	5.5 mm	5.5 mm	3.95 mm	5.5 mm	3.95 mm	3.95 mm
minfmax	80 MHz	125 MHz	125 MHz	80 MHz	80 MHz	80 MHz	80 MHz	125 MHz	80 MHz
Base Number Matches	1	1	1	1	1	1	1	1	1

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