v3.0
HiRel FPGAs
Fe a t ur es
• Low-Power 0.8µ CMOS Technology
32 0 0D X Fe a t ur es
• Highly Predictable Performance with 100% Automatic
Placement and Routing
• Device Sizes from 1,200 to 20,000 Gates
• Up to 6 Fast, Low-Skew Clock Networks
• Up to 202 User-Programmable I/O Pins
•
•
•
•
•
•
•
•
•
More Than 500 Macro Functions
Up to 1,276 Dedicated Flip-Flops
I/O Drive to 10 mA
Devices Available to DSCC SMD
CQFP and CPGA Packaging
Nonvolatile, User Programmable
Logic Fully Tested Prior to Shipment
100% Military Temperature Tested (–55°C to +125°C)
QML Certified Devices
• 100 MHz System Logic Integration
• Highest Speed FPGA SRAM, up to 2.5 kbits Configurable
Dual-Port SRAM
• Fast Wide-Decode Circuitry
• Low-Power 0.6µ CMOS Technology
12 0 0X L Fe at ure s
• Pin for Pin Compatible with ACT 2
• System Performance to 50 MHz over Military Temperature
• Low-Power 0.6µ CMOS Technology
A CT 2 Fe at ure s
• Proven Reliability Data Available
• Successful Military/Avionics Supplier for Over 10 Years
A CT 3 Fe at ure s
• Best-Value, High-Capacity FPGA Family
• System Performance to 40 MHz over Military Temperature
• Low-Power 1.0µ CMOS Technology
A CT 1 Fe at ure s
• Highest-Performance, Highest-Capacity FPGA Family
• System Performance to 60 MHz over Military Temperature
• Lowest-Cost FPGA Family
• System Performance to 20 MHz over Military Temperature
• Low-Power 1.0µ CMOS Technology
Pr od uc t F am i l y P r o f i l e
(more devices on
page 2)
Family
Device
Capacity
System Gates
Logic Gates
SRAM Bits
Logic Modules
S-Modules
C-Modules
Decode
Flip-Flops (Maximum)
User I/Os (Maximum)
Performance
System Speed (maximum)
Packages (by Pin Count)
CPGA
CQFP
3200DX
A32100DX
15,000
10,000
2,048
1,362
700
662
20
738
152
55 MHz
A32200DX
30,000
20,000
2,560
2,414
1,230
1,184
24
1,276
202
55 MHz
A1425A
3,750
2,500
NA
310
160
150
NA
435
100
60 MHz
133
132
ACT 3
A1460A
9,000
6,000
NA
848
432
416
NA
976
168
60 MHz
207
196
A14100A
15,000
10,000
NA
1,377
697
680
NA
1,493
228
60 MHz
257
256
1200XL
A1280XL
12,000
8,000
1,232
624
608
NA
998
140
50 MHz
176
172
84
208, 256
J an u a r y 2 0 0 0
1
© 2000 Actel Corporation
Pr od uc t F am i l y P r o f i l e
Family
Device
Capacity
System Gates
Logic Gates
SRAM Bits
Logic Modules
S-Modules
C-Modules
Decode
Flip-Flops (maximum)
User I/Os (maximum)
Packages (by pin count)
CPGA
CQFP
Performance
System Speed (maximum)
ACT 2
A1240A
6,000
4,000
NA
684
348
336
NA
568
104
132
—
40 MHz
A1280A
12,000
8,000
NA
1,232
624
608
NA
998
140
176
172
40 MHz
ACT 1
A1010B
1,800
1,200
NA
295
—
295
NA
147
57
84
—
A1020B
3,000
2,000
NA
547
—
547
NA
273
69
84
84
20 MHz
20 MHz
H i gh - R el i a bi l i t y , L o w - Ri s k So l ut i on
Actel builds the most reliable field programmable gate arrays
(FPGAs) in the industry, with overall antifuse reliability
ratings of less than 10 Failures-In-Time (FITs),
corresponding to a useful life of more than 40 years. Actel
FPGAs have been production proven, with more than five
million devices shipped and more than one trillion antifuses
manufactured. Actel devices are fully tested prior to
shipment, with an outgoing defect level of less than 100 ppm.
(Further reliability data is available in the
Actel Device
Reliability Report,
at
http://www.actel.com/hirel).
B en ef i t s
Mi nim i zed C os t Ri sk
junction temperatures. Actel’s non-PLD architecture delivers
lower dynamic operating current. Our reliability tests show a
very low failure rate of 6.6 FITs at 90°C junction temperature
with no degradation in AC performance. Special stress testing
at wafer test eliminates infant mortalities prior to packaging.
M ini m iz ed S e c u ri ty R is k
Reverse engineering of programmed Actel devices from
optical or electrical data is extremely difficult. Programmed
antifuses cannot be identified from a photograph or by using
an SEM. The antifuse map cannot be deciphered either
electrically or by microprobing. Each device has a silicon
signature that identifies its origins, down to the wafer lot and
fabrication facility.
M ini m ized T es ti ng Ri sk
With Actel’s line of development tools, designers can produce
as many chips as they choose for just the cost of the device
itself. There will be no NRE charges to cut into the
development budget each time a new design is tried.
M i n im i z e d T i m e R is k
After the design is entered, placement and routing is
automatic, and programming the device takes only about 5 to
15 minutes for an average design. Designers save time in the
design entry process by using tools with which they are
familiar.
Mi nim i zed R el iabi li ty R is k
Unprogrammed Actel parts are extensively tested at the
factory. Routing tracks, logic modules, and programming,
debug and test circuits are 100 percent tested before
shipment. AC performance is ensured by special speed path
tests, and programming circuitry is verified on test antifuses.
During the programming process, an algorithm is run to
ensure that all antifuses are correctly programmed. In
addition, Actel’s Silicon Explorer diagnostic tool uses
ActionProbe circuitry, allowing 100 percent observability of
all internal nodes to check and debug the design.
A c t e l FP G A De sc r i p t i o n
The PLICE antifuse is a one-time programmable, nonvolatile
connection. Since Actel devices are permanently
programmed, no downloading from EPROM or SRAM storage
is required. Inadvertent erasure is impossible, and there is no
need to reload the program after power disruptions.
Fabrication using a low-power CMOS process means cooler
The Actel families of FPGAs offer a variety of packages,
speed/performance characteristics, and processing levels for
use in all high reliability and military applications. Devices
are implemented in a silicon gate, two-level metal CMOS
process, utilizing Actel’s PLICE antifuse technology. This
2
H iR e l F PG A s
unique architecture offers gate array flexibility, high
performance, and quick turnaround through user
programming. Device utilization is typically 95 percent of
available logic modules. All Actel devices include on-chip
clock drivers and a hard-wired distribution network.
User-definable I/Os are capable of driving at both TTL and
CMOS drive levels. Available packages for the military are the
Ceramic Quad Flat Pack (CQFP) and the Ceramic Pin Grid
Array (CPGA). See the
“Product Plan” section on page 6
for
details.
Q M L C e r t i f i c at i on
A CT 3 De sc r i p t i o n
The ACT 3 family is the third-generation Actel FPGA
family. This family offers the highest-performance and
highest-capacity devices, ranging from 2,500 to 10,000 gates,
with system performance up to 60 MHz over the military
temperature range. The devices have four clock distribution
networks, including dedicated array and I/O clocks. In
addition, the ACT 3 family offers the highest I/O-to-gate ratio
available. ACT 3 devices are manufactured using 0.8µ CMOS
technology.
12 0 0X L / 32 00 D X D e sc r i p t i o n
Actel has achieved full QML certification, demonstrating
that quality management, procedures, processes, and
controls are in place and comply with MIL-PRF-38535, the
performance specification used by the Department of
Defense for monolithic integrated circuits. QML
certification is a good example of Actel's commitment to
supplying the highest quality products for all types of
high-reliability, military and space applications.
Many suppliers of microelectronics components have
implemented QML as their primary worldwide business
system. Appropriate use of this system not only helps in the
implementation of advanced technologies, but also allows
for a quality, reliable and cost-effective logistics support
throughout QML products’ life cycles.
D ev el o pm en t T oo l S up po r t
3200DX and 1200XL FPGAs were designed to integrate
system logic which is typically implemented in multiple
CPLDs, PALs, and FPGAs. These devices provide the features
and performance required for today’s complex, high-speed
digital logic systems. The 3200DX family offers the industry’s
fastest dual-port SRAM for implementing fast FIFOs, LIFOs,
and temporary data storage.
A CT 2 De sc r i p t i o n
The ACT 2 family is the second-generation Actel FPGA family.
This family offers the best-value, high-capacity devices,
ranging from 4,000 to 8,000 gates, with system performance
up to 40 MHz over the military temperature range. The
devices have two routed array clock distribution networks.
ACT 2 devices are manufactured using 1.0µ CMOS technology.
A CT 1 De sc r i p t i o n
The HiRel devices are fully supported by Actel’s line of FPGA
development tools, including the Actel DeskTOP series and
Designer Advantage tools. The Actel DeskTOP Series is an
integrated design environment for PCs that includes design
entry, simulation, synthesis, and place and route tools.
Designer Advantage is Actel’s suite of FPGA development
point tools for PCs and Workstations that includes the
ACTgen Macro Builder, Designer with DirectTime timing
driven place and route and analysis tools, and device
programming software.
In addition, the HiRel devices contain ActionProbe circuitry
that provides built-in access to every node in a design,
enabling 100 percent real-time observation and analysis of a
device’s internal logic nodes without design iteration. The
probe circuitry is accessed by Silicon Explorer, an easy to use
integrated verification and logic analysis tool that can sample
data at 100 MHz (asynchronous) or 66 MHz (synchronous).
Silicon Explorer attaches to a PC’s standard COM port,
turning the PC into a fully functional 18 channel logic
analyzer. Silicon Explorer allows designers to complete the
design verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
The ACT 1 family is the first Actel FPGA family and the first
antifuse-based FPGA. This family offers the lowest-cost logic
integration, with devices ranging from 1,200 to 2,000 gates,
with system performance up to 20 MHz over the military
temperature range. The devices have one routed array clock
distribution network. ACT 1 devices are manufactured using
1.0µ CMOS technology.
3
M i l i t a r y D e v i c e Or de r i n g I n f o r m a t i on
A14100
A
–
1
CQ
256
B
Application (Temperature Range)
C = Commercial (0 to +70°C)
M = Military (–55 to +125°C)
B = MIL-STD-883 Class B
E = Extended Flow (Space Level)
Package Lead Count
Package Type
CQ = Ceramic Quad Flat Pack (CQFP)
PG = Ceramic Pin Grid Array (CPGA)
Speed Grade
Std = Standard Speed
–1 = Approximately 15% faster than Standard
Device Revision
Part Number
A1010 =
A1020 =
A1240 =
A1280 =
A1425 =
A1460 =
A14100 =
A32100 =
A32200 =
1,200 Gates—ACT 1
2,000 Gates—ACT 1
4,000 Gates—ACT 2
8,000 Gates—ACT 2/1200XL
2,500 Gates—ACT 3
6,000 Gates—ACT 3
10,000 Gates—ACT 3
10,000 Gates—3200DX
20,000 Gates—3200DX
4
H iR e l F PG A s
D ES C SM D / A ct el P ar t N um b e r C r os s R e f e r en ce
Actel Part Number
(Gold Leads)
A1010B-PG84B
A1010B-1PG84B
A1020B-PG84B
A1020B-1PG84B
A1020B-CQ84B
A1020B-1CQ84B
A1240A-PG132B
A1240A-1PG132B
A1280A-PG176B
A1280A-1PG176B
A1280A-CQ172B
A1280A-1CQ172B
A1425A-PG133B
A1425A-1PG133B
A1425A-CQ132B
A1425A-1CQ132B
A1460A-PG207B
A1460A-1PG207B
A1460A-CQ196B
A1460A-1CQ196B
A14100A-PG257B
A14100A-1PG257B
A14100A-CQ256B
A14100A-1CQ256B
A32100DX-CQ84B
A32100DX-1CQ84B
A32200DX-CQ256B
A32200DX-1CQ256B
A32200DX-CQ208B
A32200DX-1CQ208B
DSCC SMD
(Gold Leads)
5962-9096403MXC
5962-9096404MXC
5962-9096503MUC
5962-9096504MUC
5962-9096503MTC
5962-9096504MTC
5962-9322101MXC
5962-9322102MXC
5962-9215601MXC
5962-9215602MXC
5962-9215601MYC
5962-9215602MYC
5962-9552001MXC
5962-9552002MXC
5962-9552001MYC
5962-9552002MYC
5962-9550801MXC
5962-9550802MXC
5962-9550801MYC
5962-9550802MYC
5962-9552101MXC
5962-9552102MXC
5962-9552101MYC
5962-9552102MYC
5962-9875901QXC
5962-9857902QXC
5962-9952701QXC
5962-9952702QXC
5962-9952701QYC
5962-9952702QYC
DSCC SMD
(Solder Dipped)
5962-9096403MXA
5962-9096404MXA
5962-9096503MUA
5962-9096504MUA
5962-9096503MTA
5962-9096504MTA
5962-9322101MXA
5962-9322102MXA
5962-9215601MXA
5962-9215602MXA
5962-9215601MYA
5962-9215602MYA
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
5
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