TM
HD-15530
CMOS Manchester Encoder-Decoder
Description
The Intersil HD-15530 is a high performance CMOS device
intended to service the requirements of MlL-STD-1553 and
similar Manchester II encoded, time division multiplexed
serial data protocols. This LSI chip is divided into two
sections, an Encoder and a Decoder. These sections
operate completely independent of each other, except for
the Master Reset functions.
This circuit meets many of the requirements of MIL-STD-
1553. The Encoder produces the sync pulse and the parity
bit as well as the encoding of the data bits. The Decoder
recognizes the sync pulse and identifies it as well as decod-
ing the data bits and checking parity.
This integrated circuit is fully guaranteed to support the
1MHz data rate of MlL-STD-1553 over both temperature and
voltage. It interfaces with CMOS, TTL or N channel support
circuitry, and uses a standard 5V supply.
The HD-15530 can also be used in many party line digital
data communications applications, such as an environmen-
tal control system driven from a single twisted pair cable of
fiber optic cable throughout the building.
March 1997
Features
• Support of MlL-STD-1553
• Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s
• Sync Identification and Lock-In
• Clock Recovery
• Manchester II Encode, Decode
• Separate Encode and Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE
CERDIP
TEMP. RANGE
-40
o
C to +85
o
C
-55
o
C to +125
o
C
-40
o
C to +85
o
C
-55
o
C to +125
o
C
SMD#
PDIP
-40
o
C to +85
o
C
1.25 MEGABIT/s
HD1-15530-9
HD1-15530-8
7802901JA
HD4-15530-9
HD4-15530-8
78029013A
HD3-15530-9
E24.6
J28.A
PKG. NO.
F24.6
SMD#
CLCC
Pinouts
HD-15530 (CERDIP, PDIP)
TOP VIEW
SERIAL
DATA OUT
VALID WORD 1
ENCODER
SHIFT CLK 2
TAKE DATA 3
SERIAL DATA OUT 4
DECODER CLK
5
24 V
CC
23 ENCODER CLK
22 SEND CLK IN
21 SEND DATA
20 SYNC SELECT
19 ENCODER ENABLE
18 SERIAL DATA IN
17 BIPOLAR ONE OUT
16 OUTPUT INHIBIT
BIPOLAR
15 ZERO OUT
14
÷
6 OUT
13 MASTER RESET
NC
BIPOLAR
ZERO IN
BIPOLAR
ONE IN
UNIPOLAR
DATA IN
DECODER
SHIFT CLK
7
8
9
10
11
12
COMMAND/
DATA SYNC
13
DECODER
RESET
14
GND
15
MASTER
RESET
16
17
BIPOLAR
ZERO OUT
18
OUTPUT
INHIBIT
23
22
21
20
19
NC
SYNC
SELECT
ENCODER
ENABLE
SERIAL
DATA IN
BIPOLAR
ONE OUT
DECODER
CLK
NC
5
6
HD-15530 (CLCC)
TOP VIEW
TAKE DATA
ENCODER
SHIFT CLK
ENCODER
CLK
SEND
CLK IN
27
26
25
24
SEND
DATA
NC
VALID
WORD
1
4
3
2
BIPOLAR ZERO IN 6
BIPOLAR ONE IN
7
UNIPOLAR DATA IN 8
DECODER SHIFT CLK 9
COMMAND/
DATA SYNC 10
DECODER RESET 11
GND 12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
÷
6 OUT
V
CC
28
FN2960.1
142
HD-15530
Block Diagrams
ENCODER
12
13
22
14
GND
MASTER RESET
SEND CLK IN
V
CC
OUTPUT
INHIBIT
24
UNIPOLAR 8
DATA IN
BIPOLAR 7
ONE IN
BIPOLAR 6
ZERO IN
DECODER
3
TRANSITION
FINDER
CHARACTER
IDENTIFIER
TAKE
DATA
÷
6 OUT
÷
6
ENCODER
CLK
BIT
COUNTER
÷
2
17
CHARACTER
FORMER
15
16
BIPOLAR
ONE OUT
BIPOLAR
ZERO OUT
10 COMMAND/
DATA SYNC
4 SERIAL
DATA OUT
23
DECODER
CLK
18
19
20
SYNC
SELECT
MASTER
RESET
5
SYNCHRONIZER
BIT
RATE
CLK
PARITY 1 VALID
CHECK
WORD
9
DECODER
SHIFT
CLK
13
DECODER
RESET
11
BIT
COUNTER
21
2
SEND
DATA
SERIAL
DATA IN
ENCODER
ENABLE
ENCODER
SHIFT CLK
Pin Description
PIN
NUMBER
1
2
3
4
5
TYPE
O
O
O
O
I
NAME
VALID WORD
ENCODER SHIFT
CLOCK
TAKE DATA
SERIAL DATA OUT
DECODER CLOCK
SECTION
Decoder
Encoder
Decoder
Decoder
Decoder
DESCRIPTION
Output high indicates receipt of a valid word, (valid parity and no Manches-
ter errors).
Output for shifting data into the Encoder. The Encoder samples SDI on the
low-to-high transition of Encoder Shift Clock.
Output is high during receipt of data after identification of a sync pulse and
two valid Manchester data bits.
Delivers received data in correct NRZ format.
Input drives the transition finder, and the synchronizer which in turn
supplies the clock to the balance of the decoder, input a frequency equal to
12X the data rate.
A high input should be applied when the bus is in its negative state. This pin
must be held high when the Unipolar input is used.
A high input should be applied when the bus is in its positive state. This pin
must be held low when the Unipolar input is used.
With pin 6 high and pin 7 low, this pin enters unipolar data into the transition
finder circuit. If not used this input must be held low.
Output which delivers a frequency (DECODER CLOCK
÷
12), synchro-
nized by the recovered serial data stream.
Output of a high from this pin occurs during output of decoded data which
was preceded by a Command (or Status) synchronizing character. A low
output indicates a Data synchronizing character.
A high input to this pin during a rising edge of DECODER SHIFT CLOCK
resets the decoder bit counting logic to a condition ready for a new word.
Ground Supply pin.
A high on this pin clears 2:1 counters in both Encoder and Decoder, and
resets the
÷
6 circuit.
Output from 6:1 divider which is driven by the ENCODER CLOCK.
An active low output designed to drive the zero or negative sense of a
bipolar line driver.
A low on this pin forces pin 15 and 17 high, the inactive states.
An active low output designed to drive the one or positive sense of a bipolar
line driver.
6
7
8
9
10
I
I
I
O
O
BIPOLAR ZERO IN
BIPOLAR ONE IN
UNLPOLAR DATA IN
DECODER SHIFT
CLOCK
COMMAND SYNC
Decoder
Decoder
Decoder
Decoder
Decoder
11
12
13
14
15
16
17
I
I
I
O
O
I
O
DECODER RESET
GROUND
MASTER RESET
Decoder
Both
Both
Encoder
Encoder
Encoder
Encoder
÷
6 OUT
BIPOLAR ZERO OUT
OUTPUT INHIBIT
BIPOLAR ONE OUT
143
HD-15530
Pin Description
PIN
NUMBER
18
19
20
21
22
23
24
I = Input
TYPE
I
I
I
O
I
I
I
(Continued)
NAME
SERIAL DATA IN
ENCODER ENABLE
SYNC SELECT
SEND DATA
SEND CLOCK IN
ENCODER CLOCK
V
CC
SECTION
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
Both
DESCRIPTION
Accepts a serial data stream at a data rate equal to ENCODER SHIFT
CLOCK.
A high on this pin initiates the encode cycle. (Subject to the preceeding
cycle being complete.)
Actuates a Command sync for an input high and Data sync for an input low.
An active high output which enables the external source of serial data.
Clock input at a frequency equal to the data rate X2, usually driven by
÷
6
output.
Input to the 6:1 divider, a frequency equal to the data rate X12 is usually
input here.
V
CC
is the +5V power supply pin. A 0.1µF decoupling capacitor from V
CC
(pin 24) to GROUND (pin 12) is recommended.
O = Output
Encoder Operation
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SEND CLOCK
input. An auxiliary divide by six counter is provided on chip
which can be utilized to produce the SEND CLOCK by divid-
ing the DECODER CLOCK.
The Encoder’s cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK
1
.
This cycle lasts for one word length or twenty ENCODER
SHIFT CLOCK periods. At the next low-to-high transition of
the ENCODER SHIFT CLOCK, a high SYNC SELECT input
actuates a command sync or a low will produce a data sync
for the word
2
. When the Encoder is ready to accept data,
the SEND DATA output will go high and remain high for six-
teen ENCODER SHIFT CLOCK periods
3
. During these
sixteen periods the data should be clocked into the SERIAL
DATA input with every high-to-low transition of the
ENCODER SHIFT CLOCK so it can be sampled on the low-
to-high transition
3
-
4
. After the sync and Manchester II
coded data are transmitted through the BIPOLAR ONE and
BIPOLAR ZERO outputs, the Encoder adds on an additional
bit which is the parity for that word
5
. If ENCODER
ENABLE is held high continuously, consecutive words will
be encoded without an interframe gap. ENCODER ENABLE
must go low by time
5
as shown to prevent a consecutive
word from being encoded. At any time a low on OUTPUT
INHIBIT input will force both bipolar outputs to a high state
but will not affect the Encoder in any other way.
To abort the Encoder transmission a positive pulse must be
applied at MASTER RESET. Anytime after or during this
pulse, a low-to-high transition on SEND CLOCK clears the
internal counters and initializes the Encoder for a new word.
TIMING
SEND CLK
ENCODER
SHIFT CLK
ENCODER
ENABLE
SYNC SELECT
SEND DATA
SERIAL
DATA IN
BIPOLAR
ONE OUT
BIPOLAR
ZERO OUT
1 2
0
1
2
3
4
5
6
7
15
16
17
18
19
DON’T CARE
VALID
DON’T CARE
15
1ST HALF 2ND HALF
14
15
15
14
14
13
13
13
12
12
12
11
11
11
10
3
3
3
2
2
2
1
1
1
0
0
0
P
P
SYNC
SYNC
3
4
5
FIGURE 1.
144
HD-15530
Decoder Operation
The Decoder requires a single clock with a frequency of 12
times the desired data rate applied at the DECODER
CLOCK input. The Manchester II coded data can be
presented to the Decoder in one of two ways. The BIPOLAR
ONE and BIPOLAR ZERO inputs will accept data from a
comparator sensed transformer coupled bus as specified in
Military Spec 1553. The UNIPOLAR DATA input can only
accept non-inverted Manchester II coded data. (e.g. from
BIPOLAR ONE OUT of an Encoder through an inverter to
Unipolar Data Input).
The Decoder is free running and continuously monitors its
data input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized
1
, the type of sync is indicated on
COMMAND/DATA SYNC output. If the sync character was a
command sync, this output will go high
2
and remain high
for sixteen DECODER SHIFT CLOCK periods
3
, otherwise
it will remain low. The TAKE DATA output will go high and
remain high
2
-
3
while the Decoder is transmitting the
decoded data through SERIAL DATA OUT. The decoded
data available at SERIAL DATA OUT is in NRZ format. The
DECODER SHIFT CLOCK is provided so that the decoded
bits can be shifted into an external register on every low-to-
high transition of this clock
2
-
3
. Note that DECODER
SHIFT CLOCK may adjust its phase up until the time that
TAKE DATA goes high.
After all sixteen decoded bits have been transmitted
3
the
data is checked for odd parity. A high on VALID WORD
output
4
indicates a successful reception of a word without
any Manchester or parity errors. At this time the Decoder is
looking for a new sync character to start another output
sequence. VALID WORD will go low approximately 20
DECODER SHIFT CLOCK periods after it goes high if not
reset low sooner by a valid sync and two valid Manchester
bits as shown
1
.
At any time in the above sequence a high input on
DECODER RESET during a low-to-high transition of
DECODER SHIFT CLOCK will abort transmission and initial-
ize the Decoder to start looking for a new sync character.
TIMING
DECODER
SHIFT CLK
BIPOLAR
ONE IN
BIPOLAR
ZERO IN
TAKE DATA
0
1
2
3
4
5
6
7
8
16
17
18
19
1ST HALF 2ND HALF
15
15
14
14
13
13
12
12
11
11
10
10
2
2
1
1
0
0
P
P
SYNC
SYNC
COMMAND/
DATA SYNC
SERIAL
DATA OUT
VALID WORD
UNDEFINED
(FROM PREVIOUS RECEPTION)
15
14
13
12
4
3
2
1
0
1
2
3
4
FIGURE 2.
145
HD-15530
How to Make Our MTU Look Like a Manchester Encoded UART
VALID WORD
DECODER
ENCODER CLK
1
BIPOLAR
ZERO IN
BIPOLAR
ONE IN
UNIPOLAR
DATA IN
COMMAND
SYNC
DECODER
RESET
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
BIPOLAR
ONE OUT
INHIBIT
OUTPUT
BIPOLAR
ZERO OUT
MASTER
RESET
ENCODER
ENABLE
V
CC
SYNC
SELECT
A
B
CK H
A
B
CK
74LS164
74LS164
O
H
SH/LD CK SI O
H
SH/LD CK
74165
74165
PARALLEL OUT
PARALLEL IN
FIGURE 3.
Typical Timing Diagrams for a Manchester Encoded UART
VALID
ENCODER ENABLE
SYNC SELECT
PARALLEL IN
BIPOLAR ONE OUT
BIPOLAR ZERO OUT
SYNC
MSB
LSB
P
P
PARITY
VALID
FIGURE 4. ENCODER TIMING
SYNC
BIPOLAR ONE IN
BIPOLAR ZERO IN
COMMAND SYNC
PARALLEL OUT
VALID WORD
VALID
FROM
PREVIOUS
RECEPTION
MSB
LSB
PARITY
P
P
VALID
FIGURE 5. DECODER TIMING
146
京公网安备 11010802033920号
EEWORLD
