Freescale Semiconductor
Advance Information
Document Number: MC33661
Rev. 6.0, 11/2006
Local Area Network (LIN)
Enhanced Physical Interface
with Selectable Slew Rate
Local Interconnect Network (LIN) is a serial communication protocol
designed to support automotive networks in conjunction with Controller
Area Network (CAN). As the lowest level of a hierarchical network, LIN
enables cost-effective communication with sensors and actuators
when all the features of CAN are not required.
The 33661 is a Physical Layer component dedicated to automotive
LIN sub-bus applications. It offers slew rate selection for optimized
operation at 10 kbps and 20 kbps, fast baud rate (above 100 kbps) for
test and programming modes, excellent radiated emission
performance, and safe behavior in the event of LIN bus short-to-ground
or LIN bus leakage during low-power mode.
The 33661 is compatible with LIN Protocol Specification 2.0.
Features
• Operational from V
SUP
6.0 V to 18 V DC, Functional up to 27 V DC,
and Handles 40 V During Load Dump
• Active Bus Waveshaping Offering Excellent Radiated Emission
Performance
• 5.0 kV ESD on LIN Bus Pin
• 30 kΩ Internal Pullup Resistor
• LIN Bus Short-to-Ground or High Leakage in Sleep Mode
• -18 V to +40 V DC Voltage at LIN Pin
• 8.0
µA
in Sleep Mode
• Local and Remote Wake-Up Capability Reported by INH and
RXD Pins
• 5.0 V and 3.3 V Compatible Digital Inputs Without Any External
Components Required
• Pb-Free Packaging Designated by Suffix Code EF
33661
LIN PHYSICAL INTERFACE
D SUFFIX
EF SUFFIX (PB-FREE)
98ASB42564B
8-PIN SOICN
ORDERING INFORMATION
Device
MC33661D/R2
- 40°C to 125°C
MCZ33661EF/R2
8 SOICN
Temperature
Range (T
A
)
Package
V
PWR
33661
WAKE
V
DD
Regulator
12 V
5.0
V
VSUP
INH
EN
MCU
RXD
TXD
LIN
GND
LIN Bus
Figure 1. 33661 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VSUP
WAKE
EN
INH
Control
20
µA
INH
Control
RXD
Receiver
30 kΩ
LIN
TXD
Slope
Control
GND
Figure 2. 33661 Simplified Internal Block Diagram
33661
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
RXD
EN
WAKE
TXD
1
2
3
4
8
7
6
5
INH
VSUP
LIN
GND
Figure 3. 33661 8-SOICN Pin Connections
Table 1. 33661 8-SOICN Pin Definitions
A functional description of each pin can be found in the
Functional Pin Description
section beginning on page
page 12.
Pin
1
2
3
4
5
6
7
8
Pin Name
RXD
EN
WAKE
TXD
GND
LIN
VSUP
INH
Formal Name
Data Output
Enable Control
Wake Input
Data Input
Ground
LIN Bus
Power Supply
Inhibit Output
Definition
MCU interface that reports the state of the LIN bus voltage.
Controls the operation mode of the interface.
High-voltage input used to wake up the device from Sleep mode.
MCU interface to control the state of the LIN output.
Device ground pin.
Bidirectional pin that represents the single-wire bus transmitter and receiver.
Device power supply pin.
This pin can have two main functions: controlling an external switchable voltage
regulator having an inhibit input or driving a bus external resistor in the master node
application.
33661
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
ELECTRICAL RATINGS
Power Supply Voltage
Continuous Supply Voltage
Transient Voltage (Load Dump)
WAKE DC and Transient Voltage (Through a 33 kΩ Serial Resistor)
Logic Voltage (RXD, TXD, EN Pins)
LIN Bus Voltage
DC Voltage
Transient (Coupled Through 1.0 nF Capacitor)
INH Voltage / Current
DC Voltage
DC Current
ESD Voltage
(1)
Human Body Model
All Pins
LIN Pin with Respect to Ground
Machine Model
THERMAL RATINGS
Operating Temperature
Ambient
Junction
Storage Temperature
Thermal Resistance, Junction to Ambient
Peak Package Reflow Temperature During Reflow
(2)
,
(3)
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis Temperature
T
A
T
J
T
STG
R
θ
JA
T
PPRT
T
SHUT
T
HYST
- 40 to 125
- 40 to 150
- 40 to 150
150
Note 3.
150 to 200
8.0 to 20
°C
°C/W
°C
°C
°C
°C
V
ESD2
± 2000
± 5000
± 200
V
INH
I
INH
V
ESD1
- 0.3 to V
SUP
+ 0.3
40
V
mA
V
V
WAKE
V
LOG
V
BUS
-18 to 40
-150 to 100
V
SUP
27
40
-18 to 40
- 0.3 to 5.5
V
V
V
V
Symbol
Value
Unit
Notes
1
ESD1 testing is performed in accordance with the Human Body Model (C
ZAP
= 100 pF, R
ZAP
= 1500
Ω),
ESD2 testing is performed in
accordance with the Machine Model (C
ZAP
= 220 pF, R
ZAP
= 0
Ω).
2
3.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
33661
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 7.0 V
≤
V
SUP
≤
18 V, - 40°C
≤
T
A
≤
125°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at T
A
= 25°C under nominal conditions unless otherwise noted.
Characteristic
VSUP PIN (DEVICE POWER SUPPLY)
Supply Voltage
Nominal DC
Functional DC, T
A
≥
25°C
Supply Current in Sleep Mode
V
SUP
≤
13.5 V, Recessive State
13.5 V < V
SUP
< 18 V
V
SUP
≤
13.5 V, Dominant State or Shorted to GND
Supply Current in Normal, Slow, or Fast Mode
Bus Recessive, Excluding INH Output Current
Bus Dominant, Total Bus Load > 500
Ω,
Excluding INH Output Current
RXD OUTPUT PIN (LOGIC)
Low-Level Output Voltage
I
IN
≤
1.5 mA
High-Level Output Voltage
V
EN
= 5.0 V, I
OUT
≤
250
µA
V
EN
= 3.3 V, I
OUT
≤
250
µA
TXD INPUT PIN (LOGIC)
Low-Level Input Voltage
High-Level Input Voltage
Input Threshold Voltage Hysteresis
Pullup Current Source
V
EN
= 5.0 V, 1.0 V < V
TXD
< 3.5 V
EN INPUT PIN (LOGIC)
Low-Level Input Voltage
High-Level Input Voltage
Input Voltage Threshold Hysteresis
Low-Level Input Current
V
IN
= 1.0 V
High-Level Input Current
V
IN
= 4.0 V
I
IH
—
20
40
V
IL
V
IH
V
INHYST
I
IL
5.0
20
30
µA
—
2.5
100
—
—
300
1.2
—
800
V
V
mV
µA
V
IL
V
IH
V
INHYST
I
PU
- 60
- 35
- 20
—
2.5
100
—
—
300
1.2
—
800
V
V
mV
µA
V
OH
4.25
3.0
—
—
5.25
3.5
V
OL
0
—
0.9
V
V
I
S(REC)
I
S(DOM)
—
—
4.0
6.0
6.0
8.0
I
S1
I
S2
I
S3
—
—
—
8.0
—
300
12
200
—
mA
V
SUP
7.0
6.0
13.5
—
18.0
—
µA
V
Symbol
Min
Typ
Max
Unit
33661
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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