IS43DR83200A-37CBL datasheet, PDF

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IS43DR83200A-37CBL: DescriptionDDR DRAM, 32MX8, 0.5ns, CMOS, PBGA60, 8 X 12 MM, 0.80 MM PITCH, LEAD FREE, BGA-60; Categorystorage storage; File Size1MB，54 Pages; ManufacturerIntegrated Silicon Solution ( ISSI ); Environmental Compliance

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IS43DR83200A-37CBL Overview

DDR DRAM, 32MX8, 0.5ns, CMOS, PBGA60, 8 X 12 MM, 0.80 MM PITCH, LEAD FREE, BGA-60

IS43DR83200A-37CBL Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	BGA,
Contacts	60
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Maximum access time	0.5 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B60
JESD-609 code	e1
memory density	268435456 bit
Memory IC Type	DDR DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	60
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	32MX8
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
Base Number Matches	1

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IS43DR83200A

IS43/46DR16160A, IS43DR32160A

32Mx8, 16Mx16, 16Mx32 (stacked die)

DDR2 DRAM

FEATURES

• V

= 1.8V ±0.1V, V

ddq

= 1.8V ±0.1V

• JEDEC standard 1.8V I/O (SSTL_18-compati-

ble)

• Double data rate interface: two data transfers

per clock cycle

• Differential data strobe (DQS,

DQS)

• 4-bit prefetch architecture

• On chip DLL to align DQ and DQS transitions

with CK

• 4 internal banks for concurrent operation

• Programmable CAS latency (CL) 3, 4, 5, and 6

supported

• Posted CAS and programmable additive latency

(AL) 0, 1, 2, 3, 4, and 5 supported

• WRITE latency = READ latency - 1 tCK

• Programmable burst lengths: 4 or 8

• Adjustable data-output drive strength, full and

reduced strength options

• On-die termination (ODT)

ADVANCED INFORMATION

AUGUST 2009

DESCRIPTION

ISSI's 256Mb/512Mb DDR2 SDRAM uses a double-

data-rate architecture to achieve high-speed operation.

The double-data rate architecture is essentially a

4n-prefetch architecture, with an interface designed to

transfer two data words per clock cycle at the I/O balls.

ADDRESS TABLE

Parameter

Configuration

Refresh Count

Row Addressing

Column

Addressing

Bank Addressing

Precharge

Addressing

32M x 8

8M x 8 x 4

banks

8K/64ms

1K (A0-A9)

BA0, BA1

A10

16M x 16

4M x 16 x 4

banks

8K/64ms

512 (A0-A8)

BA0, BA1

A10

16M x 32

4M x 32 x 4

banks

8K/64ms

8K (A0-A12)

512 (A0-A8)

BA0, BA1

A10

8K (A0-A12) 8K (A0-A12)

KEY TIMING PARAMETERS

Speed Grade

tRCD

tRP

tRC

tRAS

tCK @CL=3

tCK @CL=4

tCK @CL=5

tCK @CL=6

-25E

3.75

2.5

-3D

3.75

—

-37C

3.75

—

-5B

—

OPTIONS

• Configuration(s):

32Mx8 (8Mx8x4 banks) IS43DR83200A

16Mx16 (4Mx16x4 banks) IS43/46DR16160A

16Mx32 (4Mx32x4 banks) IS43DR32160A

• Package:

x8: 60-ball BGA (8mm x 12mm)

x16: 84-ball WBGA (8mm x 12.5mm)

x32: 128-ball WBGA (10.5mm x 13.5mm)

Timing – Cycle time

2.5ns @CL=6 DDR2-800E

3.0ns @CL=5 DDR2-667D

3.75ns @CL=4 DDR2-533C

5.0ns @CL=4 DDR2-400B

• Temperature Range:

Commercial (0°C

≤

85°C)

Industrial (-40°C

≤

95°C; -40°C

≤

85°C)

Automotive, A1 (-40°C

≤

95°C; -40°C

≤

85°C)

Automotive, A2 (-40°C

≤

Tc; T

≤

105°C)

Tc = Case Temp, T

= Ambient Temp

• Die Revision: A

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00B

07/28/09

IS43DR83200A-37CBL Related Products

	IS43DR83200A-37CBL	IS43DR32160A-5BBL	IS43DR83200A-5BBL	IS43DR83200A-25EBL	IS43DR32160A-37CBLI	IS43DR32160A-5BBLI	IS43DR32160A-37CBL	IS43DR83200A-3DBL
Description	DDR DRAM, 32MX8, 0.5ns, CMOS, PBGA60, 8 X 12 MM, 0.80 MM PITCH, LEAD FREE, BGA-60	DDR DRAM, 16MX32, 0.6ns, CMOS, PBGA128, 10.50 X 13.50 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, WBGA-128	DDR DRAM, 32MX8, 0.6ns, CMOS, PBGA60, 8 X 12 MM, 0.80 MM PITCH, LEAD FREE, BGA-60	DDR DRAM, 32MX8, 0.4ns, CMOS, PBGA60, 8 X 12 MM, 0.80 MM PITCH, LEAD FREE, BGA-60	DDR DRAM, 16MX32, 0.5ns, CMOS, PBGA128, 10.50 X 13.50 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, WBGA-128	DDR DRAM, 16MX32, 0.6ns, CMOS, PBGA128, 10.50 X 13.50 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, WBGA-128	DDR DRAM, 16MX32, 0.5ns, CMOS, PBGA128, 10.50 X 13.50 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, WBGA-128	DDR DRAM, 32MX8, 0.45ns, CMOS, PBGA60, 8 X 12 MM, 0.80 MM PITCH, LEAD FREE, BGA-60
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	BGA,	LFBGA,	BGA,	BGA,	LFBGA,	LFBGA,	LFBGA,	BGA,
Contacts	60	128	60	60	128	128	128	60
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compli
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
Maximum access time	0.5 ns	0.6 ns	0.6 ns	0.4 ns	0.5 ns	0.6 ns	0.5 ns	0.45 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B60	R-PBGA-B128	R-PBGA-B60	R-PBGA-B60	R-PBGA-B128	R-PBGA-B128	R-PBGA-B128	R-PBGA-B60
JESD-609 code	e1	e1	e1	e1	e1	e1	e1	e1
memory density	268435456 bit	536870912 bit	268435456 bit	268435456 bit	536870912 bit	536870912 bit	536870912 bit	268435456 bi
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	8	32	8	8	32	32	32	8
Number of functions	1	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1	1
Number of terminals	60	128	60	60	128	128	128	60
word count	33554432 words	16777216 words	33554432 words	33554432 words	16777216 words	16777216 words	16777216 words	33554432 words
character code	32000000	16000000	32000000	32000000	16000000	16000000	16000000	32000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
organize	32MX8	16MX32	32MX8	32MX8	16MX32	16MX32	16MX32	32MX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	LFBGA	BGA	BGA	LFBGA	LFBGA	LFBGA	BGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY	GRID ARRAY	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260	260	260
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
self refresh	YES	YES	YES	YES	YES	YES	YES	YES
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER	INDUSTRIAL	INDUSTRIAL	OTHER	OTHER
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	40	40	40	40	40	40	40	40
Maker	-	-	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )

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