NJ88C30 IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
NJ88C30
DS3281-1.1
NJ88C30
VHF SYNTHESISER
The NJ88C30 contains all the logic needed for a VHF PLL
synthesiser and is fabricated on the GPS high performance, small
geometry CMOS process. The circuit contains a reference oscillator
and divider, a two-modulus prescaler and 4-bit control register, a
12-bit programmable divider, a phase comparator and the
necessary data input and control logic.
GROUND
DATA TRANSFER
CLOCK
DATA
CRYSTAL MON
CRYSTAL IN
CRYSTAL OUT
1
2
3
4
5
6
7
14
13
12
COMP FREQ
f
UP
f
DN
LD
VCO
P DIV OUT
V
DD
FEATURES
s
Low Power CMOS
NJ88C30
11
10
s
s
s
s
Easy to Use
Low Cost
Single Chip Synthesiser to VHF
Lock Detect Output
9
8
DP14, MP14
APPLICATIONS
s
Mobile Radios
s
Hand Held Portable Radios
s
Sonobuoys
ORDERING INFORMATION
NJ88C30 KA DP
Plastic DIL Package
NJ88C30 KA MP
Miniature Plastic DIL Package
Fig.1 Pin connections - top view
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V
DD
Voltage on any pin
Operating temperature
Storage temperature
CRYSTAL MON
V
DD
8
14
0V
REFERENCE DIVIDER
4
1, 5, 10, 20, 2, 4, 8 OR 16
V
DD
13
COMP FREQ
20·3V
to 6V
20·3V
to V
DD
10·3V
230°C
to
170°C
255°C
to
1125°C
CRYSTAL
OUT
7
5
0V
6
CRYSTAL
IN
10
4
100
VCO
4
15/16
REF
SELECT
(DR2-DR0)
12
PHASE
COMP
0V
11
f
UP
f
DN
LOCK DETECT
(LD)
4-BIT COUNTER
12-BIT PROG DIVIDER
0V
9
0V
P DIV OUT
4-BIT REGISTER
DATA
TRANSFER
DATA
CLOCK
2
4
3
12-BIT REGISTER
3-BIT
REGISTER
19-BIT SHIFT REGISTER
1
GROUND
Fig.2 Block diagram
NJ88C30
CLOCK
DATA
DR2
DR1
DR0
DF15
DF1
DF0
DATA SET-UP TIME
DATA
TRANSFER
TRANSFER PULSE WIDTH
Fig. 4 Input data timing diagram
180
20
PHASE (DEGREES)
1M
FREQUENCY (Hz)
10M
10
GAIN (dB)
120
0
60
210
0
100k
100k
1M
FREQUENCY (Hz)
10M
Fig. 5 Gain and phase characteristics of reference oscillator inverter
CIRCUIT DESCRIPTION
Crystal Oscillator and Reference Divider
The Reference oscillator consists of a Pierce type oscillator
intended for use with a parallel resonant fundamental crystal.
Typical gain and phase characteristics for the oscillator inverter
are shown in Fig 5. An external reference oscillator may be
used by either capacitively coupling a 1V RMS sinewave into
CRYSTAL IN (pin 6) or, if CMOS levels are available, by direct
connection to CRYSTAL IN.
The reference oscillator drives a
4100
prescaler followed
by a reference divider to provide a range of comparison
frequencies which are selected by decoding the first three bits
(DR2, DR1, DR0) of the input data. The possible division ratios
and the comparison frequencies (channel spacing) if a 10MHz
crystal is used are shown in Table 1.
DR2 DR1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
DR0
0
1
0
1
0
1
0
1
Total
division
ratio
1600
800
400
200
2000
1000
500
100
Comparison frequency
for 10MHz Ref. Osc.
6·25kHz
12·5kHz
25kHz
50kHz
5kHz
10kHz
20kHz
100kHz
To assist in trimming the crystal, an open drain output at one
hundredth of the reference oscillator frequency is provided on
CRYSTAL MONITOR pin 5
Programmable Divider
The programmable divider consists of a
415/16
two modulus
prescaler with a 4-bit control register, followed by a 12-bit
programmable divider. A 1V RMS sinewave should be
capacitively coupled from the VCO to the divider input VCO pin
(pin 10).
The overall division ratio is selected by a single 16-bit word
(DF15 to DF0), loaded through the serial data bus. A lower limit
of 240 ensures correct prescaler operation; the upper limit is
65535. The VCO frequency in a locked system will be this
division ratio multiplied by the comparison frequency.
Phase Comparator
The phase comparator consists of a digital type phase
comparator with open drain
f
UP and
f
DN outputs and an
open drain LOCK DETECT (LD) output. Open drain outputs
from the reference divider and programmable divider are
provided for monitoring purposes or for use with an external
phase comparator. Waveforms for all these outputs are shown
in Fig.6. The duty cycle of
f
UP and
f
DN versus phase
difference are shown in Fig. 7. The phase comparator is linear
over a
±2π
range and if the phase gains or slips by more than
2π, the phase comparator outputs repeat with a 2π period.
Table 1 Reference divider division ratios
3