HD74ACT107RP datasheet, PDF - EEWORLD Datasheet

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HD74ACT107RP: DescriptionACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, FP-14DN; Categorylogic logic; File Size111KB，7 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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HD74ACT107RP Overview

ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, FP-14DN

HD74ACT107RP Parametric

Parameter Name	Attribute value
Parts packaging code	SOIC
package instruction	SOP,
Contacts	14
Reach Compliance Code	unknown
series	ACT
JESD-30 code	R-PDSO-G14
length	8.65 mm
Logic integrated circuit type	J-K FLIP-FLOP
Number of digits	2
Number of functions	2
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
propagation delay (tpd)	14 ns
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Trigger type	NEGATIVE EDGE
width	3.95 mm
minfmax	80 MHz
Base Number Matches	1

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HD74AC107/HD74ACT107

Dual JK Flip-Flop (with Separate Clear and Clock)

REJ03D0243–0200Z

(Previous ADE-205-363 (Z))

Rev.2.00

Jul.16.2004

Description

The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the

master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors

which connect the master and slave sections. The sequence of operation is as follows: 1) isolate slave from master; 2)

enter information from J and K inputs to master; 3) disable J and K inputs; 4) transfer information from master to slave.

Features

•

Outputs Source/Sink 24 mA

•

HD74ACT107 has TTL-Compatible Inputs

•

Ordering Information: Ex. HD74AC107

Part Name

HD74AC107FPEL

HD74AC107RPEL

Package Type

SOP-14 pin (JEITA)

Package Code Package Abbreviation Taping Abbreviation (Quantity)

FP-14DAV

EL (2,000 pcs/reel)

EL (2,500 pcs/reel)

SOP-14 pin (JEDEC) FP-14DNV

Notes: 1. Please consult the sales office for the above package availability.

2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of

the package code.

Pin Arrangement

GND 7

(Top view)

14 V

11 K

8 J

Rev.2.00, Jul.16.2004, page 1 of 6

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