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CD40106BFMSR

Description
HEX 1-INPUT INVERT GATE, CDIP14, FRIT SEALED, DIP-14
Categorylogic    logic   
File Size77KB,9 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Download Datasheet Parametric View All

CD40106BFMSR Overview

HEX 1-INPUT INVERT GATE, CDIP14, FRIT SEALED, DIP-14

CD40106BFMSR Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeDIP
package instructionDIP, DIP14,.3
Contacts14
Reach Compliance Codenot_compliant
JESD-30 codeR-GDIP-T14
JESD-609 codee0
length9.585 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeINVERTER
MaximumI(ol)0.00036 A
Number of functions6
Number of entries1
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Encapsulate equivalent codeDIP14,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5/15 V
Prop。Delay @ Nom-Sup378 ns
propagation delay (tpd)378 ns
Certification statusNot Qualified
Schmitt triggerYES
Filter levelMIL-PRF-38535 Class V
Maximum seat height5.33 mm
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
total dose100k Rad(Si) V
width7.62 mm
Base Number Matches1
CD40106BMS
December 1992
CMOS Hex Schmitt Triggers
Pinout
CD40106BMS
TOP VIEW
A 1
G=A 2
B 3
H=B 4
14 VDD
13 F
12 L = F
11 E
10 K = E
9 D
8 J=D
Features
• High Voltage Type (20V Rating)
• Schmitt Trigger Action with No External Components
• Hysteresis Voltage (Typ.)
- 0.9V at VDD = 5V
- 2.3V at VDD = 10V
- 3.5V at VDD = 15V
• Noise Immunity Greater than 50%
• No Limit on Input Rise and Fall Times
• Low VDD to VSS Current During Slow Input Ramp
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
C 5
I=C 6
VSS 7
Functional Diagram
A
1
2
G=A
B
3
4
H=B
Applications
• Wave and Pulse Shapers
• High Noise Environment Systems
• Monostable Multivibrators
C
5
6
I=C
D
9
8
J=D
E
11
10
K=E
• Astable Multivibrators
Description
CD40106BMS consists of six Schmitt trigger circuits. Each
circuit functions as an inverter with Schmitt trigger action on
the input. The trigger switches at different points for positive
and negative going signals. The difference between the
positive going voltage (VP) and the negative going voltage
(VN) is defined as hysteresis voltage (VH) (see Figure 17).
The CD40106BMS is supplied in these 14 lead outline
packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4Q
H1B
H3W
*
F
13
12
L=F
Logic Diagram
A
1 (3, 5, 9, 11, 13)
*
*
G
2 (4, 6, 8, 10, 12)
VDD
ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
FIGURE 1. 1 OF 6 SCHMITT TRIGGERS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3354
7-1327

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