PLL/Frequency Synthesis Circuit,
Parameter Name | Attribute value |
Is it Rohs certified? | conform to |
package instruction | DIP, |
Reach Compliance Code | compliant |
Analog Integrated Circuits - Other Types | PHASE LOCKED LOOP |
JESD-30 code | R-CDIP-T16 |
JESD-609 code | e4 |
length | 20.32 mm |
Humidity sensitivity level | 1 |
Number of functions | 1 |
Number of terminals | 16 |
Maximum operating temperature | 85 °C |
Minimum operating temperature | -40 °C |
Package body material | CERAMIC, METAL-SEALED COFIRED |
encapsulated code | DIP |
Package shape | RECTANGULAR |
Package form | IN-LINE |
Peak Reflow Temperature (Celsius) | 260 |
Maximum seat height | 4.69 mm |
Maximum supply voltage (Vsup) | 3.6 V |
Minimum supply voltage (Vsup) | 3 V |
Nominal supply voltage (Vsup) | 3.3 V |
surface mount | NO |
Temperature level | INDUSTRIAL |
Terminal surface | Gold (Au) - with Nickel (Ni) barrier |
Terminal form | THROUGH-HOLE |
Terminal pitch | 2.54 mm |
Terminal location | DUAL |
Maximum time at peak reflow temperature | 40 |
width | 7.62 mm |
Base Number Matches | 1 |