FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-27703-4E
ASSP
For Power Supply Applications (Lithium ion battery charger)
DC/DC Converter IC for Charging
MB3875/MB3877
s
DESCRIPTION
The MB3875 and MB3877 are charging DC/DC converter ICs suitable for down-conversion, which uses pulse
width modulation (PWM) for controlling the output voltage and current independently.
These ICs can dynamically control the secondary battery’s charge current by detecting a voltage drop in an AC
adapter in order to keep its power constant (dynamically-controlled charging).
The charging method enables quick charging, for example, with the AC adapter during operation of a notebook PC.
With an on-chip output voltage setting resistor which allows the output voltage to be set at high precision, these
ICs are best suited as internal battery chargers for notebook PCs.
The MB3875 and MB3877 support 3-cell and 4-cell batteries, respectively.
These products are covered by US Patent Number 6,147,477.
s
FEATURES
• Detecting a voltage drop in the AC adapter and dynamically controlling the charge current (Dynamically-con-
trolled charging)
• High efficiency : 95 %
• Wide range of operating supply voltages: 7 V to 25 V
• Output voltage precision (Output voltage setting resistor integrated): 0
±
0.8 % (Ta =
+
25
°C)
(Continued)
s
PACKAGE
24-pin plastic SSOP
(FPT-24P-M03)
MB3875/3877
(Continued)
• High precision reference voltage source: 4.2 V
±
0.8 %
• Support for frequency setting using an external resistor
(Frequency setting capacitor integrated) :100 kHz to 500 kHz
• On-chip current detector amplifier with wide in-phase input voltage range : 0 V to V
CC
• On-chip standby current function: 0
µA
(Typ)
• On-chip soft-start function
• Internal totem-pole output stage supporting P-channel MOS FETs devices
s
PIN ASSIGNMENT
(TOP VIEW)
−INC2
: 1
IN3 : 2
FB2 : 3
OUTC2 : 4
VREF : 5
−INE2
: 6
+INE2
: 7
+INE1
: 8
FB1 : 9
OUTC1 : 10
−INE1
: 11
−INC1
: 12
24 :
+INC2
23 : GND
22 : CS
21 : V
CC
(O)
20 : OUT
19 : VH
18 : V
CC
17 : RT
16 :
−INE3
15 : FB3
14 : CTL
13 :
+INC1
(FPT-24P-M03)
2
MB3875/3877
s
PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Symbol
–INC2
IN3
FB2
OUTC2
VREF
–INE2
+INE2
+INE1
FB1
OUTC1
–INE1
–INC1
+INC1
CTL
FB3
–INE3
RT
V
CC
VH
OUT
V
CC
(O)
CS
GND
+INC2
I/O
I
I
O
O
O
I
I
I
O
O
I
I
I
I
O
I
—
—
O
O
—
—
—
I
Descriptions
Current detection amplifier (Current Amp. 2) input pin.
DC/DC output voltage (charge voltage) input pin.
Error amplifier (Error Amp. 2) output pin.
Current detection amplifier (Current Amp. 2) output pin.
Reference voltage output pin.
Error amplifier (Error Amp. 2) inverted input pin.
Error amplifier (Error Amp. 2) non-inverted input pin.
Error amplifier (Error Amp. 1) non-inverted input pin
Error amplifier (Error Amp. 1) output pin.
Current detection amplifier (Current Amp. 1) output pin.
Error amplifier (Error Amp. 1) inverted input pin.
Current detection amplifier (Current Amp. 1) input pin.
Current detection amplifier (Current Amp. 1) input pin.
Power supply control pin.
Setting the CTL pin low places the IC in the standby mode.
Error amplifier (Error Amp. 3) output pin.
Error amplifier (Error Amp. 3) inverted input pin.
Triangular-wave oscillation frequency setting resistor connection pin.
Power supply pin for reference power supply and control circuit.
Power supply pin for FET drive circuit (VH = Vcc
−
5 V).
High-side FET gate drive pin.
Output circuit power supply.
Soft-start capacitor connection pin.
Ground pin.
Current detection amplifier (Current Amp. 2) input pin.
3
MB3875/3877
s
BLOCK DIAGRAM
−INE1
11
OUTC1
<Current Amp.1>
+
13
×
25
−INC1
−
12
+INC1
+INE1
FB1
−INE2
OUTC2
+INC2
−INC2
+INE2
8
9
6
4
24
1
7
3
10
<Error
Amp.1> VREF
−
+
<PWM
Comp.>
+
+
+
−
<Current Amp.2>
+
×
25
−
<Error
Amp.2> VREF
−
+
<OUT>
OUT
Drive
20
21
V
CC
(O)
V
CC
Bias voltage
block
19
(V
CC
−
5 V)
VH
<VH>
FB2
IN3
2
<UVLO>
V
CC
−INE3
R1
16
∗
<Error
Amp.3> VREF
−
+
+
R2
50 kΩ
(V
CC
UVLO) 215 kΩ
+
−
35 kΩ
FB3
15
<SOFT>
VREF
1
µA
VREF
(4.2 V)
0.91 V
(0.77 V)
VREF
ULVO
V
CC
CS
22
V
CC
18
CTL
2.5 V
1.5 V
<OSC>
(45 pF)
RT
17
bias
<REF>
<CTL>
14
VREF
5
GND
23
∗
: MB3875 100 kΩ
MB3877 150 kΩ
4
MB3875/3877
s
ABSOLUTE MAXIMUM RAGINGS
Parameter
Power supply voltage
Output current
Peak output current
Power dissipation
Storage temperature
Symbol
V
CC
I
OUT
I
OUT
P
D
Tstg
Ta
≤
+25°C
—
Conditions
V
CC
,V
CC
(O)
—
Duty
≤
5% (t =1 / f
OSC
×
Duty)
Rating
Min
—
—
—
—
–55
Max
28
60
500
740*
+125
Unit
V
mA
mA
mW
°C
*: The package is mounted on the dual-sided epoxy board (10 cm
×
10 cm).
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s
RECOMMENDED OPERATING CONDITIONS
Parameter
Power supply voltage
Reference voltage output
current
VH pin output current
Input voltage
CTL pin input voltage
Output current
Peak output current
Oscillator frequency
Timing resistor
Soft-start capacitor
VH pin capacitor
Reference voltage output
capacitor
Symbol
V
CC
I
REF
I
VH
V
IN
V
INE
V
INC
V
CTL
I
OUT
I
OUT
f
OSC
R
T
C
S
C
VH
C
REF
Ta
IN3
Conditions
V
CC
,V
CC
(O)
—
—
–INE1,–INE2,+INE1,+INE2
+INC1,+INC2,–INC1,–INC2,
—
—
Duty
≤
5% (t =1 / f
OSC
×
Duty)
—
—
—
—
—
—
Value
Min
7
–1
0
0
0
0
0
–45
–450
100
33
—
—
—
–30
Typ
—
—
—
—
—
—
—
—
—
290
47
2200
0.1
0.1
+25
Max
25
0
30
17
V
CC
– 1.8
V
CC
25
45
450
500
130
100000
1.0
1.0
+85
Unit
V
mA
mA
V
V
V
V
mA
mA
kHz
kΩ
pF
µF
µF
°C
Operating temperature
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5