PALCE26V12H-10JC/4 datasheet, PDF

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PALCE26V12H-10JC/4: DescriptionEE PLD, 10ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28; CategoryProgrammable logic devices Programmable logic; File Size195KB，20 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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PALCE26V12H-10JC/4 Overview

EE PLD, 10ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28

PALCE26V12H-10JC/4 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	PLASTIC, LCC-28
Reach Compliance Code	not_compliant
ECCN code	EAR99
Architecture	PAL-TYPE
maximum clock frequency	71.4 MHz
JESD-30 code	S-PQCC-J28
JESD-609 code	e0
length	11.5062 mm
Humidity sensitivity level	1
Dedicated input times	12
Number of I/O lines	12
Number of entries	26
Output times	12
Number of product terms	136
Number of terminals	28
Maximum operating temperature	75 °C
Minimum operating temperature
organize	12 DEDICATED INPUTS, 12 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC28,.5SQ
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	5 V
Programmable logic type	EE PLD
propagation delay	10 ns
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	11.5062 mm
Base Number Matches	1

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USE GAL DEVICES FOR NEW DESIGNS

FINAL

COM’L: H-7/10/15/20

IND: H-10/15/20

Lattice Semiconductor

PALCE26V12 Family

28-Pin EE CMOS Versatile PAL Device

DISTINCTIVE CHARACTERISTICS

28-pin versatile PAL programmable logic

device architecture

Electrically erasable CMOS technology

provides half power (only 115 mA) at high

speed (7.5 ns propagation delay)

14 dedicated inputs and 12 input/output

macrocells for architectural flexibility

Macrocells can be registered or combinatorial,

and active high or active low

Varied product term distribution allows up to

16 product terms per output

Two clock inputs for independent functions

Global asynchronous reset and synchronous

preset for initialization

Space-efficient 28-pin SKINNYDIP and PLCC

packages

Center VCC and GND pins to improve signal

characteristics

Extensive third-party software and programmer

support through FusionPLD partners

GENERAL DESCRIPTION

The PALCE26V12 is a 28-pin version of the popular

PAL22V10 architecture. Built with low-power, high-

speed, electrically-erasable CMOS technology, the

PALCE26V12 offers many unique advantages.

Device logic is automatically configured according to

the user’s design specification. Design is simplified by

design software, allowing automatic creation of a

programming file based on Boolean or state equations.

The software can also be used to verify the design and

can provide test vectors for the programmed device.

The PALCE26V12 utilizes the familiar sum-of-products

(AND/OR) architecture that allows users to implement

complex logic functions easily and efficiently. Multiple

levels of combinatorial logic can always be reduced

to sum-of-products form, taking advantage of the

very wide input gates available in PAL devices. The

functions are programmed into the device through

electrically-erasable floating-gate cells in the AND logic

array and the macrocells. In the unprogrammed state,

all AND product terms float HIGH. If both true and

complement of any input are connected, the term will be

permanently LOW.

The product terms are connected to the fixed OR array

with a varied distribution from 8 to 16 across the outputs

(see Block Diagram). The OR sum of the products feeds

the output macrocell. Each macrocell can be pro-

grammed as registered or combinatorial, active high or

active low, with registered I/O possible. The flip-flop can

be clocked by one of two clock inputs. The output

configuration is determined by four bits controlling three

multiplexers in each macrocell.

2-306

Publication#

16072

Rev.

Issue Date:

February 1996

Amendment

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