Hello everyone, I am a student, and I want to design a board with OMAPL138 as the core. But the information I have is quite mixed, and there is little useful information, so I want to ask if you have ...
Live event details: https://www.eeworld.com.cn/huodong/Avnet_Xilinx_Webinar_20180510/ Click to view Live date: May 10, 2018, 10:00-11:30 a.m. Live schedule: 1. Xilinx FPGA technology solutions for ADA...
To reply to the previous post, why the built-in symbol icon cannot be used, just select one of these four in menuconfig, the only difference is the size of the icon. In this way, you can select the WI...
Because the IO of the microcontroller is 5V, and the sensor signal is 24V, I hope that the sensor can cut off the signal of the optocoupler while the IO controls the optocoupler. Because the IO of the...
Question: When downloading the program using JT-LINK's SW method, what are the requirements for the high and low levels of the BOOT0 and BOOT1 pins?...
I'm working on the Viterbi decoder recently. I don't know if anyone has the manual for the viterbi core. When I call it, I get a lot of errors like Error (204009): Can't generate netlist output files ...