BUS-65153
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Card you purchase
has...
®
MIL-STD-1553B, NOTICE 2 AND
MIL-STD-1760B SMALL TERMINAL
INTERFACE CIRCUIT “STIC”
FEATURES
•
Supports MIL-STD-1553B Notice 2 and
MIL-STD-1760 Stores Management
•
Complete Intergrated Remote
Terminal Including:
•Dual
Low-Power Transceiver
•Complete
RT Protocol Logic
•
Small, 70-Pin Ceramic Package
•
Choice of 5V or 3.3V Logic Power
•
Meets 1553A/McAir Response Time
Requirements
•
Selectable 8/16-bit DMA Interface
DESCRIPTION
The BUS-65153 is a complete, dual redundant MIL-STD-1553B
Remote Terminal. Packaged in a 1.9" x 1.0" x 0.2", 70-pin ceramic
package, the BUS-65153 provides the transmitter voltage level
required by MIL-STD-1760. Also in support of MIL-STD-1760, the RT
address inputs are latchable.
The BUS-65153 contains two low power transceivers and a DDC custom
designed chip. This chip includes dual encoder/decoder, RT protocol logic, tri-
state data buffers, and DMA transfer control logic.The BUS-65153 supports all
13 dual redundant mode codes, any combination of which may be illegalized
by an external PROM, PLD, or RAM device.
Parallel data transfers are accomplished via a DMA type interface. Both 8-bit
and 16-bit transfers are supported.
The BUS-65153 can be easily interfaced to most CPU's. In addition,
the BUS-65153 can interface directly to minimum complexity subsys-
tems such as switches, D/A converters, etc.
The address bus and transfer control signals may be configured for either two-
state or three-state operation.Use of the three-state address mode reduces the
number of external components required for a DMA processor interface.
The input clock frequency is user selectable for either 12 or 16 MHz. In the
12 MHz mode, the decoder operates at 24 MHz, providing superior word error
rate and zero crossing distortion tolerance. The Busy, Service Request, and
Subsystem Flag RT Status Word bits are provided as discrete pins, allowing for
easy access by the subsystem.
Various message timing and error flag indicators are provided to facil-
itate the subsystem interface.
•
Optional Tri-State Address Bus and
Transfer Control Signals
•
Direct Interface to Simple Systems
•
Selectable Input Clock, 12 or 16 MHz
•
MIL-PRF-38535 Processing Available
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
©
2000 Data Device Corporation
A DIR
8
1
7
2
5
3
4
DT_GRT
DT_ACK
55 ohms
TX/RX A
DB_SEL
TRANSCEIVER
A
DT_REQ
BUS-25679
UPPER DATA
BUFFER
D15-D8
UPPER
DATA BUS
A XF
TX/RX A
BUS A
A XF
DATA BUS
WIDTH SELECT
Data Device Corporation
www.ddc-web.com
DMA
HANDSHAKE
HS_FAIL
BUS-25679
8
7
5
4
3
TX/RX B
2
TRANSCEIVER
B
1
TX/RX B
ENCODER/
DECODER AND
WATCHDOG
TIMER
DMA HANDSHAKE
AND TRANSFER
CONTROL LOGIC
1553
BUS
I/O
CS
WRT
DATA
TRANSFER
CONTROL
ADDR_ENA
ADDRESS
TRI-STATE
CONTROL
LOWER DATA
BUFFER
D7-D0
LOWER
DATA BUS
R.T. ADDRESS
PARITY AND
COMPARE LOGIC
A DIR
TRANSMITTER
INHIBIT
TX_INH
55 ohms
B DIR
55 ohms
B XF
BUS B
B XF
B DIR
55 ohms
CLK
CLK_SEL
2
CLOCK INPUT
AND
FREQUENCY
SELECT
RT_AD4-RT_AD0
RT_AD_P
5
ADDRESS
BUFFERS
A13-A0
14-BIT
ADDRESS
BUS
R.T.
ADDRESS
RT_AD_ERR
*
NBGRT
INCMD
GBR
ME
RT_AD_LAT
RESET
RESET
REGISTERS
AND
R.T. STATE
MACHINE
LOGIC
ILLCMD
MESSAGE
TIMING
SIGNALS
SERVICE_REQUEST
*
ILLEGALIZATION
AND STATUS
INPUTS
SSFLAG
CURRENT COMMAND,
LAST COMMAND, STATUS,
AND BIT WORD
STATUS,
ILLEGALIZATION,
AND
TRANSMITTER
INHIBIT LOGIC
RT_FAIL
BUSY
BU-65153
Rev H-07/07-0
FIGURE 1. BU-61703/5 BLOCK DIAGRAM
TABLE 1. BUS-65153 SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUN RATINGS
Supply Voltage
Logic + 5V
Transceiver + 5 V
- 15 V
- 12 V
Logic
Voltage Input Range
RECEIVER
Differential Input Resistance
(Bus-65153, Bus-65163,
BUS- 65154, Bus-65164)
(Notes 1 - 6)
Differential Input Capacitance
(Bus-65153, Bus-65163,
BUS-65154, Bus-65164)
(Notes 1 - 6)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
TRANSMITTER
Differential Output Voltage
Direct Coupled Accross 35 ohms,
Measured on Bus
Direct Coupled Accross 70 ohms
Measured on Stub
•
BUS-65153, BUS-65163 (Note 10)
•
BUS-65154, BUS-65164
Output Noise, Differential
(Direct Coupled)
Output Offset Voltage, Transformer
Coupled Accross 70 Ohms
Rise/Fall Time
LOGIC
V
IH
V
IL
I
IH
(V
IN
=V
CC
)
I
IL
(V
IN
=GND)
V
OH
(I
OH = 0)
V
OH
(I
OH = max)
V
OL
(I
OL = 0)
V
OL
(I
OL = min)
I
OL
I
OH
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
(BUS-65153, BUS-65163)
+ 5 V (Logic)
+ 5 V (CH A, CH B)
- 15 V (CH A, CH B)
Voltages/Tolerances
(BUS-65154, BUS-65164)
+ 5 V (Logic)
+ 5 V (CH A, CH B)
- 12 V (CH A, CH B)
Current Drain
(BUS-65153, BUS-65163, Note 9)
+ 5 V Logic (CH A, CH B)
- 15 V (CH A, CH B)
•
Idle
•
25% Duty Cycle
•
50% Duty Cycle
•
100% Duty Cycle
MIN
TYP
MAX
UNITS
TABLE 1. BUS-65153 SPECIFICATIONS
PARAMETER
POWER SUPPLY REQUIREMENTS
(CONTINUED)
Current Drain
(BUS-65154, BUS-65164, Note 9)
+ 5 V Logic (CH A, CH B)
- 12 V (CH A, CH B)
•
Idle
•
25% Duty Cycle
•
50% Duty Cycle
•
100% Duty Cycle
POWER DISSIPATION
BUS-65153, BUS-65163
Total Hybrid
•
Idle
•
25% Duty Cycle
•
50% Duty Cycle
•
100% Duty Cycle
Hottest Die
•
Idle
•
25% Duty Cycle
•
50% Duty Cycle
•
100% Duty Cycle
BUS-65154, BUS-65164
Total Hybrid
•
Idle
•
25% Duty Cycle
•
50% Duty Cycle
•
100% Duty Cycle
Hottest Die
•
Idle
•
25% Duty Cycle
•
50% Duty Cycle
•
100% Duty Cycle
CLOCK INPUT
Frequency
Nominal Value (Selectavle)
•
CLOCKSEL Input = Logic ‘0’
•
CLOCKSEL Input = Logic ‘1’
Long Term Tolerance
•
1553A Compliance
•
1553B Compliance
Short Term Tolerance, 1 Second
•
1553A Compliance
•
1553B Compliance
Duty Cycle
•
16 MHz
•
12 MHz
1553 MESSAGE TIMING
RT Response Time
•
16 MHz
•
12 MHz
RT-to-RT No Response Timeout
(Note 8)
Transmitter Watchdog Timeout
THERMAL
Thermal Resistance, Junction-to-
Case, Hottest Die (θJC)
BUS-65153, BUS-65163
BUS-65154, BUS-65164
Operating Junction Temperature
Storage Temperature
Lead Temperature
(Soldering for 10 seconds)
MIN
TYP
MAX
UNITS
- 0.3
- 0.5
+ 0.3
+ 0.3
- 0.5
7.0
7.0
- 18.0
- 18.0
Vcc+0.5
V
V
V
V
V
65
30
87
135
230
115
60
120
185
305
mA
mA
mA
mA
mA
11
kΩ
10
pF
0.625
0.850
1.075
1.525
0.335
0.600
0.860
1.385
1.325
1.963
2.600
3.875
0.68
1.06
1.45
2.23
W
W
W
W
W
W
W
W
0.500
0.860
10
V
P
-
P
V
PEAK
6
9
V
P
-
P
20
18
22
21
27
27
10
V
P
-
P
V
P
-
P
mV
P
-
P
,
diff
0.685
0.985
1.285
1.885
0.290
0.590
0.890
1.490
1.295
1.727
2.160
3.035
0.59
0.92
1.36
2.16
W
W
W
W
W
W
W
W
-250
100
2.0
-20
-20
Vcc+0.4
3.7
150
250
300
mV
nsec
V
V
μΑ
μΑ
V
V
V
V
mA
mA
0.8
20
20
16.0
12.0
0.01
0.1
0.001
0.01
33
40
67
60
MHz
MHz
%
%
%
%
%
%
0.4
0.5
-3.4
3.4
4.5
4.5
-15.75
5.5
5.5
-14.25
V
V
V
6.00
6.18
18.25
6.5
6.5
18.9
668
6.96
6.76
19.5
μS
μS
μS
μS
4.5
4.5
-12.6
5.5
5.5
-11.4
V
V
V
65
5
20
55
90
160
115
50
112
175
300
mA
mA
mA
mA
mA
5.54
5.54
-55
-65
160
150
+300
°C/W
°C/W
°C
°C
°C
Data Device Corporation
www.ddc-web.com
3
BU-65153
Rev H -07/07-0
TABLE 1. BUS-65153 SPECIFICATIONS
PARAMETER
PHYSICAL CHARACTERISTICS
Size
70-pin, DIP, Flat Pack
Weight
70-pin, DIP, Flat Pack
MIN
TYP
MAX
UNITS
1.9 x 1.0 x 0.215
48.26 x 25.4 x 5.46
0.6
(17)
in
(mm)
oz
(gm)
Notes: Notes 1 through 6 are applicable to the Receiver Differential
Resistance and Differential Capacitance specifications:
(1) Specifications include both transmitter and receiver (tied together
internally).
(2) Measurement of impedance is directly between pins TX/RX A(B)
and TX/RX A(B) of the BUS-65153 or BUS-65163 hybrid.
(3) Assuming the connection of all power and ground inputs to the
hybrid.
(4) The specifications are applicable for both unpowered and powered
conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 KHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are
guaranteed,but not tested, over the operating range.
(7) Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to pins of the isolation transformer on the stub side
(either direct or transformer coupled), referenced to hybrid ground. Use
a DDC recommended transformer or other transformer that provides an
equivalent minimum CMRR.
(8) RT-to-RT Timeout is measured from the Mid-Parity crossing of the
Transmit Command word to the Mid-Sync crossing of the Transmitting
RT Status word.
(9) Current drain is for total hybrid (e.g., +5V supply current includes
the sum of logic +5V supply current, channel A +5V supply current and
channel B +5V supply current). Transmitting duty cycles assume one
channel transmitting and alternate channel idle.
(10) Compliant with 1760 applications.
Any subset of the possible 1553 commands (broadcast, T/R bit,
subaddress, word count/mode code) may be optionally illegal-
ized by means of an external PROM, PAL, or RAM device. An
extensive amount of message validation is performed for each
message received. Each word received is validated for correct
sync type and sync encoding, Manchester II encoding, parity,
and bit count. All messages are verified to contain a legal,
defined Command Word and correct word count. If the BUS-
65153 is the receiving RT in an RT-to-RT transfer, it verifies that
the T/R bit of the transmit Command Word is a one and that the
transmitting RT responds in time and contains the correct RT
address in its Status Word.
The 65153 may be operated from either a 12 MHz or 16 MHz
clock input. In the 12 MHz mode, the decoder samples incoming
data with
both
edges of the clock input. This, in effect, provides
for 24 MHz decoder sampling. Benefits of the higher sampling
rate include a wider tolerance for zero-crossing distortion and
improved bit error rate performance.
The BUS-65153 includes a hardwired R.T. address input. This
includes 5 address lines, an address parity input, and an address
parity error output. The RT address can also be latched internal-
ly by means of the address latching input signal RT_ADD_LAT.
The 65153 supports command illegalization. Commands may be
illegalized
by
asserting
the
output
signal
ILLCMD low approximately 5 ms after the mid-parity bit zero-
crossing of the received Command Word. Command Words may
be illegalized as a function of broadcast, T/R bit, subaddress,
word count and/or mode code.
An internal Built-in-Test (BIT) Word register is updated at the end
of each message. The contents of the BIT Word Register are
transmitted in response to a Transmit BIT Word Mode Command.
The BUS-65153 provides a number of real-time output signals.
These various signals provide indications of message start, mes-
sage in progress, valid received message, message error, hand-
shake fail, and looptest fail or transmitter timeout.
The BUS-65153 may be used in a wide variety of interface con-
figurations. The 65153 has an 8/16-bit tri-state data bus and an
address/control bus that may be pin programmed for either two-
state or three-state operation. The three-state mode allows the
BUS-65153 to be connected directly to the host processor's
data, address, and control buses in a DMA configuration. The
BUS-65153 includes standard DMA handshake signals
(Request, Grant, and Acknowledge) as well as transfer control
outputs (CS and WRT). The DMA interface may operate in either
a 16-bit or 8-bit mode, supporting both word-wide and byte-wide
transfers.
The DMA interface also allows the 65153 to be interfaced direct-
ly to a simple system that doesn't have a microprocessor. This
provides a low-cost 1553 interface for A/D and D/A converters,
switch closures, and actuators.
The BUS-65153 may also be used in a shared RAM interface
configuration. By means of tri-state buffers and a very small
amount of “glue” logic, the 65153 will store Command Words and
access Data Words to/from dedicated “mailbox” areas in a
shared RAM for each broadcast / T-R bit / subaddress / mode
code.
INTRODUCTION
GENERAL
The BUS-65153 is a complete MIL-STD-1553 Remote Terminal
(RT) bus interface unit. Contained in the hybrid are a dual trape-
zoidal transceiver and Manchester II encoder/decoder, and
Remote Terminal (RT) protocol logic for MIL-STD-1553B. Also
included are built-in self-test capability and a parallel subsystem
interface. The subsystem interface includes a 14-bit address bus
and a data bus that may be configured for either 8-bit or 16-bit
DMA transfers.
The transceiver front end of the BUS-65153 is implemented by
means of low-power bipolar analog monolithic and thick-film
hybrid technology. The transceiver requires +5 V and -15 V only
(no +15 V is required) and includes voltage source transmitters.
The voltage source transmitters provide superior line driving
capability for long cables and heavy amounts of bus loading. In
addition, the monolithic transceivers provide a minimum stub
voltage level of 20 volts peak-to-peak transformer coupled, mak-
ing the BUS-65153 suitable for MIL-STD-1760 applications.
The receiver sections of the BUS-65153 are fully compliant with
MIL-STD-1553B in terms of front end overvoltage protection,
threshold and bit-error rate.
The BUS-65153 implements all MIL-STD-1553 message for-
mats, including all 13 of the 1553B dual redundant mode codes.
Data Device Corporation
www.ddc-web.com
4
BU-65153
Rev H-07/07-0
If a more elaborate shared RAM interface is needed, the BUS-
65153 may be interfaced to a BUS-66315 memory management
unit. If a BUS-66315 is used, the address bus of the BUS-65153
is not used for accessing the system RAM (although the address
outputs may still be used for command illegalizing).
The BUS-66315 provides an RT Lookup Table, allowing the map-
ping of the various T-R/subaddresses to user programmable
areas in the BUS-66315's 64K x 16 shared RAM address space.
The BUS-66315 also provides a stack area of RAM. The stack
provides a chronology of all messages processed, storing a
Block Status Word (message channel, completion, and validity
information), an optional Time Tag Word and the received
Command Word for each message processed. The BUS-66315
also provides maskable interrupts to the host processor for end-
of-message and/or message error conditions.
An 8/16-bit data bus, a 14-bit address bus, and six control sig-
nals are provided to facilitate communication with the parallel
subsystem. The control signals include the standard DMA hand-
shake signals DT_REQ, DT_GRT, DT_ACK as well as the trans-
fer control outputs CS and WRT. HS_FAIL provides an indication
to the subsystem of a handshake failure condition.
Data is transferred between the subsystem and the BUS-65153
via a DMA handshake, initiated by the BUS-65153. A READ
operation is defined to be the transfer of data from the subsys-
tem to the BUS-65153. Conversely, a WRITE operation transfers
data from the BUS-65153 to the subsystem.
If the BUS-65153 is in 16-bit mode, data is transferred as a sin-
gle 16-bit word. In 8-bit mode, data is transferred in a pair of byte
transfers within the same DMA handshake cycle. The upper byte
is transferred first with A0=1, followed by the lower byte with
A0=0.
ADDRESS MAPPING
The memory allocation scheme for the BUS-65153 14-bit
address bus is defined as follows:
A13:
A12:
A11-A7:
A6:
A5-A1:
A0:
BROADCAST/OWNADDRESS
TRANSMIT/RECEIVE
SUBADDRESS 4-0
DATA/COMMAND
WORD COUNT/CURRENT WORD COUNT
UPPER/LOWER BYTE (8-bit mode only)
HANDSHAKE FAIL
If the BUS-65153 (STIC) asserts DT_REQ and the subsystem
does not respond with DT_GRT in time for the BUS-65153 to
complete the word transfer, the HS_FAIL output will be asserted
low to inform the subsystem of the handshake failure and bit D12
in the internal Built-In-Test (BIT) word is set to logic ©1." If the
handshake failure occurs on a data word read transfer (transmit
command) the STIC will abort the current message processing
and
NOT
transmit erroneous data back to the bus controller. In
the case of a handshake failure on a write transfer (receive com-
mand word transfer, transmit command transfer, or a receive
data word transfer) the STIC will set the handshake failure out-
put and BIT word bit, and continue processing the current mes-
sage.
The method of address mapping implemented by the BUS-
65153 provides for a “mailbox” allocation scheme for the storage
of Command and Data Words. The address outputs A13 through
A1 map directly into 8K words (16K bytes) of processor address
space. A0 is used for upper/lower byte selection in the 8-bit DMA
mode. The same address map is applicable for both the DMA
and shared RAM (without the BUS-66315) interface configura-
tions. The BUS-65153's addressing scheme maps messages in
terms of broadcast/own address, transmit/receive, subaddress,
and mode code. A 64-word message block is allocated for each
T/R-subaddress.
The received Command Word for all nonmode code messages is
stored at relative word location zero (0) within the respective
message block. For mode code messages, the address for the
received Command Word is offset from location zero (0) within
the message block for subaddress 0 or 31. The value of the
address offset is equal to the mode code field of the respective
Command Word (0 to 31).
For nonmode code messages, the Data Words to be transmitted
or received are accessed from (to) relative locations 32 through
63 within the message block. For mode code messages with a
single Data Word that is not read from internal register, the
address for the Data Word is offest from location 32 within the
64-word message block for subaddresses 0 and 31. The value of
the address offset is equal to the mode code field of the received
Command Word.
The Data Words transmitted in response to Transmit Last
Command or Transmit BIT Word mode commands are accessed
from a pair of internal registers.
DMA READ OPERATION
Whenever the BUS-65153 needs to read a word from the sub-
system, it asserts the signal DT_REQ low. If the subsystem
asserts DT_GRT in time, the BUS-65153 will then assert A13
through A1 (and A0 for the 8-bit mode), WRT high, along with
DT_ACK and CS low to enable data from the subsystem.
After the transfer of each Data Word has been completed,
address bus outputs A5 through A1 are incremented. This pro-
vides the option of connecting the BUS-65153 address lines
directly to the host processor's address bus to access the sub-
system RAM, if desired.
DMA WRITE OPERATION
Whenever the BUS-65153 needs to transfer data to the subsys-
tem, it initiates a DMA WRITE cycle. The BUS-65153 asserts
DT_REQ. The subsystem must respond with DT_GRT.
If DT_GRT was received in time, the BUS-65153 will then assert
DT_ACK. The BUS-65153 will then assert A13 through A1 (and
A0 in 8-bit mode) and WRT low, followed by CS low. The sub-
system may then use the rising edge of CS to latch the data.
Similar to the DMA read operation, the address outputs A5
through A1 are incremented after the completion of a DMA
WRITE operation.
DMA INTERFACE
Data Device Corporation
www.ddc-web.com
5
BU-65153
Rev H -07/07-0
DSP and ARM Processors
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