MPC8280CVRB datasheet, PDF - EEWORLD Datasheet

Freescale Semiconductor

Technical Data

MPC8280EC

Rev. 1.7, 12/2006

MPC8280

PowerQUICC II™ Family

Hardware Specifications

This document contains detailed information about power

considerations, DC/AC electrical characteristics, and AC timing

specifications for .13µm (HiP7) members of the

PowerQUICC II™ family of integrated communications

processors—the MPC8280, the MPC8275, and the MPC8270

(collectively called 'the MPC8280' throughout this document).

Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 7

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 8

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 11

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

AC Electrical Characteristics . . . . . . . . . . . . . . . . . . 14

Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 24

Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 73

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 76

Document Revision History . . . . . . . . . . . . . . . . . . . 76

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

Overview

1

Overview

Table 1. MPC8280 PowerQUICC II Family Functionality

Devices

Functionality

MPC8270

Package

1

480 TBGA

Serial communications controllers (SCCs)

QUICC multi-channel controller (QMC)

Fast communication controllers (FCCs)

I-Cache (Kbyte)

D-Cache (Kbyte)

Ethernet (10/100)

UTOPIA II Ports

Multi-channel controllers (MCCs)

PCI bridge

Transmission convergence (TC) layer

Inverse multiplexing for ATM (IMA)

Universal serial bus (USB) 2.0 full/low rate

Security engine (SEC)

1

Table 1

shows the functionality supported by each device in the MPC8280 family.

MPC8275

516 PBGA

4

—

3

16

3

2

1

Yes

—

1

—

MPC8280

480 TBGA

4

—

3

16

3

2

Yes

1

—

516 PBGA

4

—

3

16

3

0

1

Yes

—

1

—

4

—

3

16

3

0

1

Yes

—

1

—

Refer to

Table 2.

Devices in the MPC8280 family are available in three packages—the standard ZU package and the alternate VR or

ZQ packages—as shown in

Table 2.

Note that throughout this document references to the MPC8280 and the

MPC8270 are inclusive of VR and ZQ package devices unless otherwise specified. For more information on VR and

ZQ packages, contact your Freescale sales office. For package ordering information, refer to

Section 10, “Ordering

Information.”

Table 2. HiP7 PowerQUICC II Device Packages

Code

(Package)

Device

MPC8270

MPC8270VR

MPC8270ZQ

ZU

(480 TBGA—Leaded)

MPC8280

VR

(516 PBGA—Lead free)

MPC8275VR

ZQ

(516 PBGA—Lead spheres)

MPC8275ZQ

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

2

Freescale Semiconductor

Overview

Figure 1

shows the block diagram. Shaded portions are device-specific; refer to the notes below.

16 Kbytes

I-Cache

I-MMU

G2_LE Core

System Interface Unit

(SIU)

16 Kbytes

D-Cache

D-MMU

Bus Interface Unit

60x-to-PCI

Bridge

60x-to-Local

Bridge

Memory Controller

Serial

DMAs

4 Virtual

IDMAs

Clock Counter

System Functions

60x Bus

PCI Bus

32 bits, up to 66 MHz

or

Local Bus

32 bits, up to 100 MHz

Communication Processor Module (CPM)

Timers

Parallel I/O

Baud Rate

Generators

Interrupt

Controller

32 KB

Instruction

RAM

32 KB

Data

RAM

32-bit RISC Microcontroller

and Program ROM

IMA

1

Microcode

MCC1

1

MCC2

FCC1

FCC2

FCC3

SCC1

SCC2

SCC3

SCC4/

USB

SMC1

SMC2

SPI

I

2

C

TC Layer Hardware1

Time Slot Assigner

Serial Interface2

8 TDM Ports2

3 MII or RMII

Ports

2 UTOPIA

Ports3

Non-Multiplexed

I/O

Notes:

1

MPC8280 only (not

on MPC8270,

the VR package, nor the ZQ package)

2

MPC8280 has 2 serial interface (SI) blocks and 8 TDM ports. MPC8270 and the VR and ZQ packages have

only 1 SI block and 4 TDM ports (TDM2[A–D]).

3

MPC8280, MPC8275VR, MPC8275ZQ only (not

on MPC8270,

MPC8270VR, nor MPC8270ZQ)

Figure 1. MPC8280 Block Diagram

1.1 Features

The major features of the MPC8280 are as follows:

•

Dual-issue integer (G2_LE) core

— A core version of the EC603e microprocessor

— System core microprocessor supporting frequencies of 166–450 MHz

— Separate 16-Kbyte data and instruction caches:

– Four-way set associative

– Physically addressed

– LRU replacement algorithm

— Architecture-compliant memory management unit (MMU)

— Common on-chip processor (COP) test interface

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

3

Overview

•

— High-performance (SPEC95 benchmark at 450 MHz; 855 Dhrystones MIPS at 450 MHz)

— Supports bus snooping for data cache coherency

— Floating-point unit (FPU)

Separate power supply for internal logic and for I/O

Separate PLLs for G2_LE core and for the CPM

— G2_LE core and CPM can run at different frequencies for power/performance optimization

— Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1, 7:1, 8:1 ratios

— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios

64-bit data and 32-bit address 60x bus

— Bus supports multiple master designs

— Supports single- and four-beat burst transfers

— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

— Supports data parity or ECC and address parity

32-bit data and 18-bit address local bus

— Single-master bus, supports external slaves

— Eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

60x-to-PCI bridge

— Programmable host bridge and agent

— 32-bit data bus, 66.67/83.3/100 MHz, 3.3 V

— Synchronous and asynchronous 60x and PCI clock modes

— All internal address space available to external PCI host

— DMA for memory block transfers

— PCI-to-60x address remapping

PCI bridge

— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz

— On-chip arbitration

— Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming

— PCI host bridge or periphera

l

capabilities

— Includes 4 DMA channels for the following transfers:

– PCI-to-60x to 60x-to-PCI

– 60x-to-PCI to PCI-to-60x

– PCI-to-60x to PCI-to-60x

– 60x-to-PCI to 60x-to-PCI

— Includes all of the configuration registers (which are automatically loaded from the EPROM and used

to configure the MPC8280) required by the PCI standard as well as message and doorbell registers

— Supports the I

2

O standard

— Hot-swap friendly (supports the hot swap specification as defined by PICMG 2.1 R1.0 August 3, 1998)

— Support for 66.67/83.33/100 MHz, 3.3 V specification

— 60x-PCI bus core logic that uses a buffer pool to allocate buffers for each port

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

4

Freescale Semiconductor

Overview

•

— Uses the local bus signals, removing need for additional pins

System interface unit (SIU)

— Clock synthesizer

— Reset controller

— Real-time clock (RTC) register

— Periodic interrupt timer

— Hardware bus monitor and software watchdog timer

— IEEE 1149.1 JTAG test access port

12-bank memory controller

— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user- definable

peripherals

— Byte write enables and selectable parity generation

— 32-bit address decodes with programmable bank size

— Three user-programmable machines, general-purpose chip-select machine, and page-mode pipeline

SDRAM machine

— Byte selects for 64-bus width (60x) and byte selects for 32-bus width (local)

— Dedicated interface logic for SDRAM

CPU core can be disabled and the device can be used in slave mode to an external core

Communications processor module (CPM)

— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for

communications protocols

— Interfaces to G2_LE core through an on-chip 32-Kbyte dual-port data RAM, an on-chip 32-Kbyte

dual-port instruction RAM and DMA controller

— Serial DMA channels for receive and transmit on all serial channels

— Parallel I/O registers with open-drain and interrupt capability

— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers

— Three fast communications controllers supporting the following protocols:

– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII)

or reduced media independent interface (RMII)

– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1, AAL0

protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64 K external connections (no ATM

support for the MPC8270)

– Transparent

– HDLC—Up to T3 rates (clear channel)

– FCC2 can also be connected to the TC layer (MPC8280 only)

— Two multichannel controllers (MCCs) (one MCC on the MPC8270)

– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split into four

subgroups of 32 channels each.

– Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up

to four TDM interfaces per MCC

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

5

MPC8280CVRB

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