Advance Information
MPC850EC/D
Rev. 0.2, 04/2002
MPC850 (Rev. A/B/C)
Communications Controller
Hardware Specifications
This document contains detailed information on power considerations, AC/DC electrical
characteristics, and AC timing specifications for revision A,B, and C of the MPC850.
This document contains the following topics:
Topic
Page
Part I, “Overview”
Part II, “Features”
Part III, “Electrical and Thermal Characteristics”
Part IV, “Thermal Characteristics”
Part V, “Power Considerations”
Part VI, “Bus Signal Timing”
Part VII, “IEEE 1149.1 Electrical Specifications”
Part VIII, “CPM Electrical Characteristics”
Part IX, “Mechanical Data and Ordering Information”
Part X, “Document Revision History”
1
3
7
8
9
10
37
39
61
67
Part I Overview
The MPC850 is a versatile, one-chip integrated microprocessor and peripheral combination
that can be used in a variety of controller applications, excelling particularly in
communications and networking products. The MPC850, which includes support for
Ethernet, is specifically designed for cost-sensitive, remote-access, and telecommunications
applications. It is provides functions similar to the MPC860, with system enhancements such
as universal serial bus (USB) support and a larger (8-Kbyte) dual-port RAM.
In addition to a high-performance embedded MPC8xx core, the MPC850 integrates system
functions, such as a versatile memory controller and a communications processor module
(CPM) that incorporates a specialized, independent RISC communications processor
(referred to as the CP). This separate processor off-loads peripheral tasks from the embedded
MPC8xx core.
The CPM of the MPC850 supports up to seven serial channels, as follows:
•
One or two serial communications controllers (SCCs). The SCCs support Ethernet,
ATM (MPC850SAR), HDLC and a number of other protocols, along with a
transparent mode of operation.
•
•
•
•
One USB channel
Two serial management controllers (SMCs)
One I
2
C port
One serial peripheral interface (SPI).
Table 1 shows the functionality supported by the members of the MPC850 family.
Table 1. MPC850 Functionality Matrix
Part
MPC850
MPC850DE
MPC850SAR
Number of
SCCs
Supported
1
2
2
Ethernet
Support
Yes
Yes
Yes
ATM Support
-
-
Yes
USB Support
Yes
Yes
Yes
Number of
Multi-channel
PCMCIA Slots
HDLC Support
Supported
-
-
Yes
1
1
1
Additional documentation may be provided for parts listed in Table 1.
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MPC850 (Rev. A/B/C) Hardware Specifications
MOTOROLA
Part II Features
Figure 1 is a block diagram of the MPC850, showing its major components and the relationships among
those components:
2-Kbyte
I-Cache
Embedded
MPC8xx
Core
Instruction
Bus
Instruction
MMU
1-Kbyte
D-Cache
Load/Store
Bus
Data
MMU
System Interface Unit
Memory Controller
Unified Bus
Bus Interface Unit
System Functions
Real-Time Clock
PCMCIA Interface
Baud Rate
Generators
Parallel I/O
Ports
—
UTOPIA
(850SAR)
Four
Timers
Interrupt
Controller
Dual-Port
RAM
20 Virtual
Serial DMA
Channels
and
2 Virtual
IDMA
Channels
Peripheral Bus
Communications
Processor
Module
32-Bit RISC Communications
Processor (CP) and Program ROM
Timer
SCC2
TDMa
SCC3
SMC1
SMC2
USB
SPI
I
2
C
Time Slot Assigner
Non-Multiplexed Serial Interface
Figure 1. MPC850 Microprocessor Block Diagram
The following list summarizes the main features of the MPC850:
•
Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— Performs branch folding and branch prediction with conditional prefetch, but without
conditional execution
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
3
— 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture)
– Caches are two-way, set-associative
– Physically addressed
– Cache blocks can be updated with a 4-word line burst
– Least-recently used (LRU) replacement algorithm
– Lockable one-line granularity
— Memory management units (MMUs) with 8-entry translation lookaside buffers (TLBs) and
fully-associative instruction and data TLBs
— MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and
8 Mbytes; 16 virtual address spaces and eight protection groups
•
•
Advanced on-chip emulation debug mode
Data bus dynamic bus sizing for 8, 16, and 32-bit buses
— Supports traditional 68000 big-endian, traditional x86 little-endian and modified little-endian
memory systems
— Twenty-six external address lines
•
•
Completely static design (0–80 MHz operation)
System integration unit (SIU)
— Hardware bus monitor
— Spurious interrupt monitor
— Software watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
•
Memory controller (eight banks)
— Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM
(SDRAM), static random-access memory (SRAM), electrically programmable read-only
memory (EPROM), flash EPROM, etc.
— Memory controller programmable to support most size and speed memory interfaces
— Boot chip-select available at reset (options for 8, 16, or 32-bit memory)
— Variable block sizes, 32 Kbytes to 256 Mbytes
— Selectable write protection
— On-chip bus arbiter supports one external bus master
— Special features for burst mode support
•
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
4
MPC850 (Rev. A/B/C) Hardware Specifications
MOTOROLA
— Interrupt can be masked on reference match and event capture
•
Interrupts
— Eight external interrupt request (IRQ) lines
— Twelve port pins with interrupt capability
— Fifteen internal interrupt sources
— Programmable priority among SCCs and USB
— Programmable highest-priority request
•
Single socket PCMCIA-ATA interface
— Master (socket) interface, release 2.1 compliant
— Single PCMCIA socket
— Supports eight memory or I/O windows
•
Communications processor module (CPM)
— 32-bit, Harvard architecture, scalar RISC communications processor (CP)
— Protocol-specific command sets (for example,
GRACEFUL STOP TRANSMIT
stops transmission
after the current frame is finished or immediately if no frame is being sent and
CLOSE RXBD
closes the receive buffer descriptor)
— Supports continuous mode transmission and reception on all serial channels
— Up to 8 Kbytes of dual-port RAM
— Twenty serial DMA (SDMA) channels for the serial controllers, including eight for the four
USB endpoints
— Three parallel I/O registers with open-drain capability
•
Four independent baud-rate generators (BRGs)
— Can be connected to any SCC, SMC, or USB
— Allow changes during operation
— Autobaud support option
•
Two SCCs (serial communications controllers)
— Ethernet/IEEE 802.3, supporting full 10-Mbps operation
— HDLC/SDLC™ (all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk
®
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
•
QUICC multichannel controller (QMC) microcode features
— Up to 64 independent communication channels on a single SCC
— Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
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