MT46V8M16TG-6TL datasheet, PDF

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MT46V8M16TG-6TL: DescriptionDDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP-66; Categorystorage storage; File Size6MB，81 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT46V8M16TG-6TL Overview

DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP-66

MT46V8M16TG-6TL Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micron Technology
Parts packaging code	TSOP
package instruction	TSOP2, TSSOP66,.46
Contacts	66
Reach Compliance Code	not_compliant
ECCN code	EAR99
Is Samacsys	N
access mode	FOUR BANK PAGE BURST
Maximum access time	0.7 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PDSO-G66
JESD-609 code	e0
length	22.22 mm
memory density	134217728 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	66
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSSOP66,.46
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.003 A
Maximum slew rate	0.385 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm
Base Number Matches	1

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128Mb: x4, x8, x16 DDR SDRAM

Features

Double Data Rate (DDR) SDRAM

MT46V32M4 – 8 Meg x 4 x 4 Banks

MT46V16M8 – 4 Meg x 8 x 4 Banks

MT46V8M16 – 2 Meg x 16 x 4 Banks

Features

• V

= +2.5V ±0.2V, V

Q = +2.5V ±0.2V

• V

= +2.6V ±0.1V, V

Q = +2.6V ±0.1V (DDR400)

• Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data

capture (x16 has two – one per byte)

• Internal, pipelined double-data-rate (DDR)

architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask (DM) for masking write data

(x16 has two – one per byte)

• Programmable burst lengths: 2, 4, or 8

• Auto refresh and self refresh modes

• Longer lead TSOP for improved reliability (OCPL)

• 2.5V I/O (SSTL_2 compatible)

• Concurrent auto precharge option is supported

•

RAS lockout supported (

RAP =

RCD)

Options

• Configuration

–

32 Meg x 4 (8 Meg x 4 x 4 banks)

–

16 Meg x 8 (4 Meg x 8 x 4 banks)

–

8 Meg x 16 (2 Meg x 16 x 4 banks)

• Plastic package – OCPL

–

66-pin TSOP

–

66-pin TSOP (Pb-free)

• Timing – cycle time

–

5ns @ CL = 3 (DDR400)

–

6ns @ CL = 2.5 (DDR333)

(TSOP only)

–

7.5ns @ CL = 2 (DDR266)

–

7.5ns @ CL = 2 (DDR266A)

–

7.5ns @ CL = 2.5 (DDR266B)

• Self refresh

–

Standard

–

Low-power self refresh

• Temperature rating

–

Commercial (0°C to 70°C)

–

Industrial (–40°C to +85°C)

• Revision

Marking

32M4

16M8

8M16

-5B

-6T

-75E

-75Z

-75

None

Notes: 1. Not recommended for new designs

Table 1:

Key Timing Parameters

CL = CAS (READ) latency; MIN clock rate with 50% duty cycle at CL = 2 (-75E, -75Z), CL = 2.5 (-6, -6T, -75), and

CL = 3 (-5B)

Clock Rate (MHz)

Speed Grade

-5B

-6T

-75E/-75Z

-75

CL = 2

133

100

CL = 2.5

167

133

CL = 3

200

n/a

Data Out

Window

1.6ns

2.0ns

2.5ns

Access

Window

±0.70ns

±0.75ns

DQS–DQ

Skew

+0.40ns

+0.45ns

+0.50ns

PDF: 09005aef816fd013/Source: 09005aef82a95a3a

128Mb_DDR_x4x8x16_D1.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mb: x4, x8, x16 DDR SDRAM

Table of Contents

State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Electrical Specifications – I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Electrical Specifications – DC and AC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

LOAD MODE REGISTER (LMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

ACTIVE (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

PRECHARGE (PRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

BURST TERMINATE (BST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

AUTO REFRESH (AR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

REGISTER DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

POWER-DOWN (CKE Not Active). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

PDF: 09005aef816fd013/Source: 09005aef82a95a3a

128Mb_DDRTOC.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mb: x4, x8, x16 DDR SDRAM

Functional Description

The DDR SDRAM uses a double data rate architecture to achieve high-speed operation.

The double data rate architecture is essentially a 2n-prefetch architecture with an inter-

face designed to transfer two data words per clock cycle at the I/O pins. A single read or

write access for the DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-

cycle data transfer at the internal DRAM core and two corresponding

n-bit

wide, one-

half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in

data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during

READs and by the memory controller during WRITEs. DQS is edge-aligned with data for

READs and center-aligned with data for WRITEs. The x16 offering has two data strobes,

one for the lower byte and one for the upper byte.

The DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK

going HIGH and CK# going LOW will be referred to as the positive edge of CK.

Commands (address and control signals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and output data is referenced to both

edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a

selected location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command, which may then

be followed by a READ or WRITE command. The address bits registered coincident with

the ACTIVE command are used to select the bank and row to be accessed. The address

bits registered coincident with the READ or WRITE command are used to select the bank

and the starting column location for the burst access.

The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8

locations. An AUTO PRECHARGE function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst access.

As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs

allows for concurrent operation, thereby providing high effective bandwidth by hiding

row precharge and activation time.

An auto refresh mode is provided, along with a power-saving power-down mode. All

inputs are compatible with the JEDEC standard for SSTL_2. All full-drive option outputs

are SSTL_2, Class II compatible.

General Notes

• The functionality and the timing specifications discussed in this data sheet are for the

DLL-enabled mode of operation.

• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ

term is to be interpreted as any and all DQ collectively, unless specifically stated

otherwise. Additionally, the x16 is divided into two bytes, the lower byte and upper

byte. For the lower byte (DQ0–DQ7) DM refers to LDM and DQS refers to LDQS. For

the upper byte (DQ8–DQ15) DM refers to UDM and DQS refers to UDQS.

• Complete functionality is described throughout the document and any page or

diagram may have been simplified to convey a topic and may not be inclusive of all

requirements.

• Any specific requirement takes precedence over a general statement.

PDF: 09005aef816fd013/Source: 09005aef82a95a3a

DDR_x4x8x16_Core1.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT46V8M16TG-6TL Related Products

	MT46V8M16TG-6TL	MT46V8M16TG-6T:D	MT46V8M16TG-6TIT	MT46V16M8P-6TIT	MT46V16M8TG-6T:D	MT46V8M16P-5B:D	MT46V16M8TG-6TL	MT46V16M8TG-6TIT	MT46V8M16P-6T:D	MT46V8M16P-6TL
Description	DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP-66	DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP-66	DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP-66	DDR DRAM, 16MX8, 0.7ns, CMOS, PDSO66, 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66	DDR DRAM, 16MX8, 0.7ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP-66	DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66	DDR DRAM, 16MX8, 0.7ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP-66	DDR DRAM, 16MX8, 0.7ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP-66	DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66	DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP-66
Is it Rohs certified?	incompatible	incompatible	incompatible	conform to	incompatible	conform to	incompatible	incompatible	conform to	conform to
Parts packaging code	TSOP	TSOP	TSOP	TSOP	TSOP	TSOP	TSOP	TSOP	TSOP	TSOP
package instruction	TSOP2, TSSOP66,.46	TSSOP, TSSOP66,.46	TSOP2, TSSOP66,.46	TSSOP, TSSOP66,.46	TSSOP, TSSOP66,.46	TSSOP, TSSOP66,.46	0.400 INCH, PLASTIC, TSOP-66	0.400 INCH, PLASTIC, TSOP-66	TSSOP, TSSOP66,.46	TSOP2, TSSOP66,.46
Contacts	66	66	66	66	66	66	66	66	66	66
Reach Compliance Code	not_compliant	not_compliant	not_compliant	compliant	not_compliant	unknown	not_compliant	not_compliant	unknown	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	0.7 ns	0.7 ns	0.7 ns	0.7 ns	0.7 ns	0.7 ns	0.7 ns	0.7 ns	0.7 ns	0.7 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	166 MHz	167 MHz	166 MHz	167 MHz	166 MHz	200 MHz	167 MHz	167 MHz	167 MHz	166 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
interleaved burst length	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8
JESD-30 code	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66
JESD-609 code	e0	e0	e0	e3	e0	e3	e0	e0	e3	e3
length	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm
memory density	134217728 bit	134217728 bit	134217728 bit	134217728 bit	134217728 bit	134217728 bit	134217728 bit	134217728 bit	134217728 bit	134217728 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	16	16	16	8	8	16	8	8	16	16
Number of functions	1	1	1	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1	1	1	1
Number of terminals	66	66	66	66	66	66	66	66	66	66
word count	8388608 words	8388608 words	8388608 words	16777216 words	16777216 words	8388608 words	16777216 words	16777216 words	8388608 words	8388608 words
character code	8000000	8000000	8000000	16000000	16000000	8000000	16000000	16000000	8000000	8000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	85 °C	85 °C	70 °C	70 °C	70 °C	85 °C	70 °C	70 °C
organize	8MX16	8MX16	8MX16	16MX8	16MX8	8MX16	16MX8	16MX8	8MX16	8MX16
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSSOP	TSOP2	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSOP2
Encapsulate equivalent code	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	235	235	260	235	260	NOT SPECIFIED	NOT SPECIFIED	260	260
power supply	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.6 V	2.5 V	2.5 V	2.5 V	2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	4096	4096	4096	4096	4096	4096	4096	4096	4096	4096
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
Continuous burst length	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8
Maximum standby current	0.003 A	0.003 A	0.003 A	0.003 A	0.003 A	0.003 A	0.003 A	0.003 A	0.003 A	0.003 A
Maximum slew rate	0.385 mA	0.385 mA	0.385 mA	0.355 mA	0.355 mA	0.385 mA	0.355 mA	0.355 mA	0.385 mA	0.385 mA
Maximum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.5 V	2.3 V	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.6 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Matte Tin (Sn)	Tin/Lead (Sn/Pb)	Matte Tin (Sn)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	30	30	30	30	30	NOT SPECIFIED	NOT SPECIFIED	30	30
width	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm
Maker	Micron Technology	Micron Technology	Micron Technology	-	-	-	Micron Technology	Micron Technology	Micron Technology	Micron Technology
Base Number Matches	1	1	1	1	1	1	-	-	-	-

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