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EP20K400EFI784-3

Description
Loadable PLD, PBGA784
CategoryProgrammable logic devices    Programmable logic   
File Size781KB,65 Pages
ManufacturerAltera (Intel)
Download Datasheet Parametric View All

EP20K400EFI784-3 Overview

Loadable PLD, PBGA784

EP20K400EFI784-3 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerAltera (Intel)
package instructionBGA,
Reach Compliance Codecompliant
Is SamacsysN
JESD-30 codeS-PBGA-B784
JESD-609 codee0
Humidity sensitivity level3
Dedicated input times4
Number of terminals784
organize4 DEDICATED INPUTS
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Programmable logic typeLOADABLE PLD
Certification statusNot Qualified
Maximum supply voltage2.625 V
Minimum supply voltage2.375 V
Nominal supply voltage2.5 V
surface mountYES
Terminal surfaceTIN LEAD
Terminal formBALL
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
Base Number Matches1
APEX 20K
®
Programmable Logic
Device Family
Data Sheet
May 1999, ver. 2
Features...
s
Preliminary
Information
s
Industry’s first programmable logic device (PLD) incorporating
System-on-a-Programmable-Chip
TM
integration
MultiCore
TM
architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
Embedded system block (ESB) implementation of product-term
logic used for combinatorial-intensive functions
LUT logic used for register-intensive functions
ESB used to implement memory functions, including first-in
first-out (FIFO) buffers, dual-port RAM, and content-
addressable memory (CAM)
High density
100,000 to 1 million typical gates (see Table 1)
Up to 42,240 logic elements (LEs)
Up to 540,672 RAM bits that can be used without reducing
available logic
Up to 4,224 product-term-based macrocells
Table 1. APEX 20K Device Features
Feature
Maximum
system gates
Typical gates
LEs
ESBs
Maximum
RAM bits
Maximum
macrocells
Maximum
user I/O pins
Notes:
(1)
(2)
Notes (1), (2)
EP20K100E EP20K160E EP20K200E EP20K300E EP20K400E EP20K600E EP20K1000E
EP20K100
EP20K200
EP20K400
263,000
106,000
4,160
26
53,248
416
252
404,000
163,000
6,400
40
81,920
640
320
526,000
211,000
8,320
52
106,496
832
382
728,000
293,000
11,520
72
147,456
1,152
420
1,052,000
423,000
16,640
104
212,992
1,664
502
1,537,000
618,000
24,320
152
311,296
2,432
620
2,670,000
1,073,000
42,240
264
540,672
4,224
780
The embedded IEEE Std. 1149.1 JTAG boundary-scan circuitry contributes up to 52,130 additional gates.
This information is preliminary.
Altera Corporation
A-DS-APEX20K-02
23
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