Changes to Ordering Guide .......................................................... 25
3/01—Revision 0: Initial Version
Rev. A | Page 2 of 24
ADF4206/ADF4208
SPECIFICATIONS
V
DD
1 = V
DD
2 = 3 V ± 10%, 5 V ± 10%; V
DD
1, V
DD
2 ≤ V
P
1, V
P
2 ≤ 6.0 V; AGND
RF1
= DGND
RF1
= AGND
RF2
= DGND
RF2
= 0 V;
T
A
= T
MIN
to T
MAX
, unless otherwise noted; dBm referred to 50 Ω.
Table 1.
Parameter
RF/IF CHARACTERISTICS (3 V)
RF1 Input Frequency (RF1
IN
)
ADF4206
ADF4208
RF Input Sensitivity
IF Input Frequency (RF2
IN
)
ADF4206
ADF4208
IF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency
3
RF CHARACTERISTICS (5 V)
RF1 Input Frequency (RF1
IN
)
ADF4206
ADF4208
RF Input Sensitivity
IF Input Frequency (RF2
IN
)
ADF4206
ADF4208
IF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency
3
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity
4
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency
5
CHARGE PUMP
I
CP
Sink/Source
High Value
Low Value
Absolute Accuracy
I
CP
Three-State Leakage Current
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
/I
INL
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
B Version
1
B Chips
2
Unit
Test Conditions/Comments
See Figure 22 for input circuit
For f < 50 MHz ensure SR > 23 V/μs
For f < 50 MHz ensure SR > 37 V/μs
0.05/0.55
0.08/2.0
–15/+4
0.05/0.55
0.08/1.1
−15/+4
165
0.05/0.55
0.08/2.0
−15/+4
0.05/0.55
0.08/1.1
−15/+4
165
GHz min/max
GHz min/max
dBm min/max
GHz min/max
GHz min/max
dBm min/max
MHz max
For f < 50 MHz ensure SR > 23 V/μs
For f < 50 MHz ensure SR > 37 V/μs
0.05/0.55
0.08/2.0
−10/+4
0.05/0.55
0.08/1.1
−10/+4
200
0.05/0.55
0.08/2.0
−10/+4
0.05/0.55
0.08/1.1
–10/+4
200
GHz min/max
GHz min/max
dBm min/max
MHz min/max
GHz min/max
GHz min/max
dBm min/max
MHz max
For f < 50 MHz ensure SR > 32 V/μs
For f < 50 MHz ensure SR > 51 V/μs
For f < 50 MHz ensure SR > 32 V/μs
For f < 50 MHz ensure SR > 51 V/μs
5/40
−2
10
±100
55
5/40
−2
10
±100
55
MHz min/max
dBm min
pF max
μA max
MHz max
For f < 5 MHz ensure SR > 9 V/μs
5
1.25
2.5
1
0.8 × V
DD
0.2 × V
DD
±1
10
V
DD
− 0.4
0.4
5
1.25
2.5
1
0.8 × V
DD
0.2 × V
DD
±1
10
V
DD
− 0.4
0.4
mA typ
mA typ
% typ
nA typ
V min
V max
μA max
pF max
V min
V max
I
OH
= 500 μA
I
OL
= 500 μA
Rev. A | Page 3 of 24
ADF4206/ADF4208
Parameter
POWER SUPPLIES
V
DD
1
V
DD
2
V
P
I
DD
(I
DD
1 + I
DD
2)
6
ADF4206
ADF4208
I
DD
1
ADF4206
ADF4208
I
DD
2
ADF4206
ADF4208
I
P
(I
P
1 + I
P
2)
Low Power Sleep Mode
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(RF1)
7
ADF4206
ADF4208
Phase Noise Performance
8
ADF4206 (RF1, RF2)
ADF4208 (RF1)
ADF4208 (RF1)
Spurious Signals
RF1, RF2 (20 kHz Loop B/W)
1
2
B Version
1
2.7/5.5
V
DD
1
V
DD
1/6.0
14
21
8
14
7.5
9
1
0.5
B Chips
2
2.7/5.5
V
DD
1
V
DD
1/6.0
14
21
8
14
7.5
9
1
0.5
Unit
V min/V max
V min/V max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
μA typ
Test Conditions/Comments
V
DD
1, V
DD
2 ≤ V
P
1, V
P
2 ≤ 6.0 V
9.5 mA typical at V
DD
= 3 V, T
A
= 25°C
14 mA typical at V
DD
= 3 V, T
A
= 25°C
5.5 mA typical at V
DD
= 3 V, T
A
= 25°C
9 mA typical at V
DD
= 3 V, T
A
= 25°C
5 mA typical at V
DD
= 3 V, T
A
= 25°C
5.5 mA typical at V
DD
= 3 V, T
A
= 25°C
T
A
= 25°C
−213
−217
−92
−85
−91
−80/−84
−213
−217
−92
−85
−91
−80/−84
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dB typ
@ VCO output
@ 540 MHz output, 200 kHz at PFD
@ 1750 MHz output, 200 kHz at PFD
@ 900 MHz output, 200 kHz at PFD
@ 200 kHz/400 kHz offsets and
200 kHz PFD
Operating temperature range for B version: −40°C to +85°C.
The B chip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
4
AC coupling ensures AV
DD
/2 bias. V
DD
1 = V
DD
2 = 3 V; For V
DD
1 = V
DD
2 = 5 V, use CMOS-compatible levels.
5
Guaranteed by design. Sample tested to ensure compliance.
6
Typical values apply for V
DD
= 3 V; P = 32; RF1
IN
1/RF2
IN
2 for ADF4206 = 540 MHz; RF1
IN
1/RF2
IN
2 for ADF4208 = 900 MHz.
7
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log F
PFD
. PN
SYNTH
= PN
TOT
− 10 log F
PFD
− 20 log N.
8
The phase noise is measured at 1 kHz, unless otherwise noted. The phase noise is measured with the EVAL-ADF4206EB or the EVAL-ADF4208EB evaluation board and
the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer (f
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GD32 MCU
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