EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

E1SJA14-20.35625M TR

Description
Quartz Crystal Resonator HC49/UP Short 2 Pad Surface Mount (SMD) 3.2mm Height Metal Resistance Weld Seal 20.35625MHz ±15ppm/30ppm over -40°C to +85°C
CategoryPassive components    Crystal/resonator   
File Size542KB,4 Pages
ManufacturerECLIPTEK
Websitehttp://www.ecliptek.com
Environmental Compliance
Download Datasheet Parametric Compare View All

E1SJA14-20.35625M TR Overview

Quartz Crystal Resonator HC49/UP Short 2 Pad Surface Mount (SMD) 3.2mm Height Metal Resistance Weld Seal 20.35625MHz ±15ppm/30ppm over -40°C to +85°C

E1SJA14-20.35625M TR Parametric

Parameter NameAttribute value
Brand NameEcliptek
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeSMD HC-49/UP Short
Contacts2
Manufacturer packaging codeSMD HC-49/UP Short
Reach Compliance Code163
Ageing5 PPM/YEAR
Base Number Matches1

E1SJA14-20.35625M TR Related Products

E1SJA14-20.35625M TR E1SJA14-20.35625M
Description Quartz Crystal Resonator HC49/UP Short 2 Pad Surface Mount (SMD) 3.2mm Height Metal Resistance Weld Seal 20.35625MHz ±15ppm/30ppm over -40°C to +85°C Quartz Crystal Resonator HC49/UP Short 2 Pad Surface Mount (SMD) 3.2mm Height Metal Resistance Weld Seal 20.35625MHz ±15ppm/30ppm over -40°C to +85°C
Brand Name Ecliptek Ecliptek
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Parts packaging code SMD HC-49/UP Short SMD HC-49/UP Sh
Contacts 2 2
Manufacturer packaging code SMD HC-49/UP Short SMD HC-49/UP Sh
Reach Compliance Code 163 compli
Ageing 5 PPM/YEAR 5 PPM/YEAR
Base Number Matches 1 1
Initial hardware design, need some information about OMAPL138
Hello everyone, I am a student, and I want to design a board with OMAPL138 as the core. But the information I have is quite mixed, and there is little useful information, so I want to ask if you have ...
流誓星空 TI Technology Forum
Live Q&A Highlights: Xilinx and Avnet focus on embedded vision applications to support artificial intelligence and assisted driving!
Live event details: https://www.eeworld.com.cn/huodong/Avnet_Xilinx_Webinar_20180510/ Click to view Live date: May 10, 2018, 10:00-11:30 a.m. Live schedule: 1. Xilinx FPGA technology solutions for ADA...
EEWORLD社区 FPGA/CPLD
[ESP32-S2-Kaluga-1 Review] 6. Packing up, the end of the LGVL lighting interface
To reply to the previous post, why the built-in symbol icon cannot be used, just select one of these four in menuconfig, the only difference is the size of the icon. In this way, you can select the WI...
RCSN Domestic Chip Exchange
Can this diagram be used in this way?
Because the IO of the microcontroller is 5V, and the sensor signal is 24V, I hope that the sensor can cut off the signal of the optocoupler while the IO controls the optocoupler. Because the IO of the...
sky999 PCB Design
About downloading programs using emulator
Question: When downloading the program using JT-LINK's SW method, what are the requirements for the high and low levels of the BOOT0 and BOOT1 pins?...
深圳小花 MCU
Calling the Viterbi kernel
I'm working on the Viterbi decoder recently. I don't know if anyone has the manual for the viterbi core. When I call it, I get a lot of errors like Error (204009): Can't generate netlist output files ...
'Friday Altera SoC

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号