LD3985
SERIES
ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE
REGULATORS LOW ESR CAPACITORS COMPATIBLE
s
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INPUT VOLTAGE FROM 2.5V TO 6V
STABLE WITH LOW ESR CERAMIC
CAPACITORS
ULTRA LOW DROPOUT VOLTAGE (100mV
TYP. AT 150mA LOAD, 0.4mV TYP. AT 1mA
LOAD)
VERY LOW QUIESCENT CURRENT (85µA
TYP. AT NO LOAD, 170µA TYP. AT 150mA
LOAD; MAX 1.5µA IN OFF MODE)
GUARANTEED OUTPUT CURRENT UP TO
150mA
WIDE RANGE OF OUTPUT VOLTAGE: 1.2V;
1.22V; 1.25V; 1.35V; 1.5V; 1.8V; 2V; 2.1V;
2.2V; 2.4V; 2.5V; 2.6V; 2.7V; 2.8V; 2.85V;
2.9V; 3V; 3.1V; 3.2V; 3.3V; 4.7V; 5V
FAST TURN-ON TIME: TYP. 200µs [C
O
=1µF,
C
BYP
= 10nF AND I
O
=1mA]
LOGIC-CONTROLLED ELECTRONIC
SHUTDOWN
INTERNAL CURRENT AND THERMAL LIMIT
OUTPUT LOW NOISE VOLTAGE 30µVRMS
OVER 10Hz to 100KHz
S.V.R. OF 60dB AT 1KHz, 50dB AT 10KHz
TEMPERATURE RANGE: -40°C TO 125°C
Flip-Chip
(1.57x1.22)
SOT23-5L
TSOT23-5L
DESCRIPTION
The LD3985 provides up to 150mA, from 2.5V to
6V input voltage.
Figure 1: Schematic Diagram
The ultra low drop-voltage, low quiescent current
and low noise make it suitable for low power
applications and in battery powered systems.
Regulator ground current increases only slightly in
dropout, further prolonging the battery life. Power
supply rejection is better than 60 dB at low
frequencies and starts to roll off at 10KHz. High
power supply rejection is maintained down to low
input voltage levels common to battery operated
circuits. Shutdown Logic Control function is
available, this means that when the device is used
as local regulator, it is possible to put a part of the
board in standby, decreasing the total power
consumption. The LD3985 is designed to work
with low ESR ceramic capacitors. Typical
applications are in mobile phone and similar
battery powered wireless systems.
October 2004
Rev. 8
1/14
LD3985 SERIES
Table 1: Absolute Maximum Ratings
Symbol
V
I
V
O
V
INH
I
O
P
D
T
STG
T
OP
DC Input Voltage
DC Output Voltage
INHIBIT Input Voltage
Output Current
Power Dissipation
Storage Temperature Range
Operating Junction Temperature Range
Parameter
Value
-0.3 to 6 (*)
-0.3 to V
I
+0.3
-0.3 to V
I
+0.3
Internally limited
Internally limited
-65 to 150
-40 to 125
°C
°C
Unit
V
V
V
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
(*) The input pin is able to withstand non repetitive spike of 6.5V for 200ms.
Table 2: Thermal Data
Symbol
Parameter
SOT23-5L/
TSOT23-5L
81
255
170
Flip-Chip
Unit
°C/W
°C/W
R
thj-case
Thermal Resistance Junction-case
R
thj-amb
Thermal Resistance Junction-ambient
Table 3: Order Codes
SOT23-5L
LD3985M12R (*)
LD3985M122R
LD3985M125R (*)
LD3985M135R (*)
LD3985M15R
LD3985M18R
LD3985M20R (*)
LD3985M21R (*)
LD3985M22R (*)
LD3985M24R (*)
LD3985M25R
LD3985M26R (*)
LD3985M27R
LD3985M28R (*)
LD3985M285R (*)
LD3985M29R
LD3985M30R (*)
LD3985M31R (*)
LD3985M32R (*)
LD3985M33R
LD3985M44R (*)
LD3985M47R
LD3985M48R (*)
LD3985M49R (*)
LD3985M50R (*)
(*) Available on request.
TSOT23-5L
LD3985G12R (*)
LD3985G122R (*)
LD3985G125R (*)
LD3985G135R (*)
LD3985G15R (*)
LD3985G18R
LD3985G20R (*)
LD3985G21R (*)
LD3985G22R (*)
LD3985G24R (*)
LD3985G25R
LD3985G26R (*)
LD3985G27R
LD3985G28R (*)
LD3985G285R (*)
LD3985G29R
LD3985G30R (*)
LD3985G31R (*)
LD3985G32R (*)
LD3985G33R (*)
LD3985G44R (*)
LD3985G47R (*)
LD3985G48R (*)
LD3985G49R (*)
LD3985G50R (*)
Flip-Chip
LD3985J12R (*)
LD3985J122R
LD3985J125R
LD3985J135R
LD3985J15R (*)
LD3985J18R
LD3985J20R (*)
LD3985J21R (*)
LD3985J22R (*)
LD3985J24R
LD3985J25R
LD3985J26R
LD3985J27R
LD3985J28R
LD3985J285R (*)
LD3985J29R
LD3985J30R
LD3985J31R
LD3985J32R (*)
LD3985J33R
LD3985J44R (*)
LD3985J47R
LD3985J48R
LD3985J49R (*)
LD3985J50R (*)
OUTPUT VOLTAGES
1.20 V
1.22 V
1.25 V
1.35 V
1.5 V
1.8 V
2.0 V
2.1 V
2.2 V
2.4 V
2.5 V
2.6 V
2.7 V
2.8 V
2.85 V
2.9 V
3.0 V
3.1 V
3.2 V
3.3 V
4.4 V
4.7 V
4.8 V
4.9 V
5.0 V
2/14
LD3985 SERIES
Figure 2: Connection Diagram
(top view for SOT and TSOT, top through view for Flip-Chip)
TSOT23-5L/SOT23-5L
Flip-Chip
Table 4: Pin Description
Pin N°
SOT23-5L/
TSOT23-5L
1
2
3
4
5
Pin N°
Flip-Chip
4
2
1
5
3
Symbol
V
I
GND
V
INH
BYPASS
V
O
Input Voltage of the LDO
Common Ground
Inhibit Input Voltage: ON MODE when V
INH
≥
1.2V, OFF MODE when V
INH
≤
0.4V (Do not leave floating, not internally pulled down/up)
Bypass Pin: Connect an external capacitor (usually 10nF) to minimize noise
voltage
Output Voltage of the LDO
Name and Function
Figure 3: Typical Application Circuit
3/14
LD3985 SERIES
Symbol
C
O
Parameter
Output Capacitor
Test Conditions
Capacitance (Note 6)
ESR
Min.
1
5
Typ.
Max.
22
5000
Unit
µF
mΩ
Note 1 – For V
O(NOM)
< 2V, V
I
= 2.5V
Note 2 – For V
O(NOM)
= 1.25V, V
I
= 2.5V
Note 3 – Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This speci-
fication does not apply for input voltages below 2.5V.
Note 4 – Turn-on time is time measured between the enable input just exceeding V
INH
High Value and the output voltage just reaching 95%
of its nominal value
Note 5 – Typical thermal protection hysteresis is 20°C
Note 6 - The minimum capacitor value is 1µF, anyway the LD3985 is still stable if the compensation capacitor has a 30% tolerance in all
temperature range.
TYPICAL PERFORMANCE CHARACTERISTICS
(T
j
= 25°C, V
I
= V
O(NOM)
+0.5V, C
I
= C
O
= 1µF,
C
BYP
= 10nF, I
O
= 1mA, V
INH
= 1.4V, unless otherwise specified)
Figure 4:
Output Voltage vs Temperature
Figure 6:
Output Voltage vs Temperature
Figure 5:
Output Voltage vs Temperature
Figure 7:
Shutdown Voltage vs Temperature
5/14
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