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NC7SZ00L6X

Description
LVC/LCX/Z SERIES, 2-INPUT NAND GATE, PDSO6
Categorylogic    logic   
File Size132KB,9 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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NC7SZ00L6X Overview

LVC/LCX/Z SERIES, 2-INPUT NAND GATE, PDSO6

NC7SZ00L6X Parametric

Parameter NameAttribute value
Brand NameFairchild Semiconduc
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeMICROPAK MLP
package instruction1 MM, MO-252UAAD, MICROPACK-6
Contacts6
Manufacturer packaging code6LD, MICROPAK, JEDEC MO-252, 1.0MM WIDE - MLP (PREMOLDED)
Reach Compliance Codeunknow
ECCN codeEAR99
seriesLVC/LCX/Z
JESD-30 codeR-PDSO-N6
JESD-609 codee4
length1.45 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of functions1
Number of entries2
Number of terminals6
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeVSON
Encapsulate equivalent codeSOLCC6,.04,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, VERY THIN PROFILE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Su5.2 ns
propagation delay (tpd)12 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height0.55 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)1.65 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width1 mm
Base Number Matches1
NC7SZ00 TinyLogic£ UHS 2-Input NAND Gate
October 1996
Revised February 2005
NC7SZ00
TinyLogic£ UHS 2-Input NAND Gate
General Description
The NC7SZ00 is a single 2-Input NAND Gate from
Fairchild's Ultra High Speed Series of TinyLogic
£
. The
device is fabricated with advanced CMOS technology to
achieve ultra high speed with high output drive while main-
taining low static power dissipation over a broad V
CC
oper-
ating range. The device is specified to operate over the
1.65V to 5.5V V
CC
operating range. The inputs and output
are high impedance when V
CC
is 0V. Inputs tolerate volt-
ages up to 6V independent of V
CC
operating voltage.
Features
Space saving SOT23 or SC70 5-lead package
Ultra small MicroPak
¥
Pb-Free leadless package
Ultra High Speed; t
PD
2.4 ns typ into 50 pF at 5V V
CC
High Output Drive;
r
24 mA at 3V V
CC
Broad V
CC
Operating Range; 1.65V–5.5V
Matches the performance of LCX when operated at
3.3V V
CC
Power down high impedance inputs/output
Overvoltage tolerant inputs facilitate 5V to 3V translation
Patented noise/EMI reduction circuitry implemented
Ordering Code:
Order Number
NC7SZ00M5X
NC7SZ00M5_NL
(Note 1)
NC7SZ00M5X_NL
(Note 2)
NC7SZ00P5X
NC7SZ00P5_NL
(Note 1)
NC7SZ00P5X_NL
(Note 2)
NC7SZ00L6X
Package
Number
MA05B
MA05B
MA05B
MAA05A
MAA05A
MAA05A
MAC06A
Product Code
Top Mark
7Z00
7Z00
7Z00
Z00
Z00
Z00
YY
Package Description
5-Lead SOT23, JEDEC MO-178, 1.6mm
Pb-Free 5-Lead SOT23, JEDEC MO-178,
1.6mm
Pb-Free 5-Lead SOT23, JEDEC MO-178,
1.6mm
5-Lead SC70, EIAJ SC-88a, 1.25mm Wide
5-Lead SC70, EIAJ SC-88a, 1.25mm Wide
5-Lead SC70, EIAJ SC-88a, 1.25mm Wide
Pb-Free 6-Lead MicroPak, 1.0mm Wide
Supplied As
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
5k Units on Tape and Reel
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates lead-free product (per JEDEC J-STD-020B).
Note 2:
“_NL” indicates lead-free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only.
TinyLogic
£
is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS012156
www.fairchildsemi.com

NC7SZ00L6X Related Products

NC7SZ00L6X NC7SZ00 NC7SZ00_05 NC7SZ00M5_NL NC7SZ00P5X_NL NC7SZ00M5X_NL
Description LVC/LCX/Z SERIES, 2-INPUT NAND GATE, PDSO6 LVC/LCX/Z SERIES, 2-INPUT NAND GATE, PDSO5 LVC/LCX/Z SERIES, 2-INPUT NAND GATE, PDSO5 LVC/LCX/Z SERIES, 2-INPUT NAND GATE, PDSO5 LVC/LCX/Z SERIES, 2-INPUT NAND GATE, PDSO5 LVC/LCX/Z SERIES, 2-INPUT NAND GATE, PDSO5
series LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z
Number of functions 1 1 1 1 1 1
Number of terminals 6 5 5 5 5 5
Maximum operating temperature 85 °C 85 Cel 85 Cel 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 Cel -40 Cel -40 °C -40 °C -40 °C
surface mount YES Yes Yes YES YES YES
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal form NO LEAD GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL
Is it Rohs certified? conform to - - conform to conform to conform to
Parts packaging code MICROPAK MLP - - SOIC SOIC SOIC
package instruction 1 MM, MO-252UAAD, MICROPACK-6 - - LSSOP, TSOP5/6,.11,37 TSSOP, TSSOP5/6,.08 LSSOP, TSOP5/6,.11,37
Contacts 6 - - 5 5 5
Reach Compliance Code unknow - - compli compli compli
JESD-30 code R-PDSO-N6 - - R-PDSO-G5 R-PDSO-G5 R-PDSO-G5
JESD-609 code e4 - - e3 e3 e3
length 1.45 mm - - 2.9 mm 2 mm 2.9 mm
Load capacitance (CL) 50 pF - - 50 pF 50 pF 50 pF
Logic integrated circuit type NAND GATE - - NAND GATE NAND GATE NAND GATE
MaximumI(ol) 0.024 A - - 0.024 A 0.024 A 0.024 A
Humidity sensitivity level 1 - - 1 1 1
Number of entries 2 - - 2 2 2
Package body material PLASTIC/EPOXY - - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code VSON - - LSSOP TSSOP LSSOP
Encapsulate equivalent code SOLCC6,.04,20 - - TSOP5/6,.11,37 TSSOP5/6,.08 TSOP5/6,.11,37
Package shape RECTANGULAR - - RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, VERY THIN PROFILE - - SMALL OUTLINE, LOW PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 - - 260 260 260
power supply 3.3 V - - 3.3 V 3.3 V 3.3 V
Prop。Delay @ Nom-Su 5.2 ns - - 5.2 ns 5.2 ns 5.2 ns
propagation delay (tpd) 12 ns - - 12 ns 12 ns 12 ns
Certification status Not Qualified - - Not Qualified Not Qualified Not Qualified
Schmitt trigger NO - - NO NO NO
Maximum seat height 0.55 mm - - 1.4 mm 1.1 mm 1.4 mm
Maximum supply voltage (Vsup) 5.5 V - - 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 1.65 V - - 1.65 V 1.65 V 1.65 V
Nominal supply voltage (Vsup) 1.8 V - - 1.8 V 1.8 V 1.8 V
technology CMOS - - CMOS CMOS CMOS
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au) - - Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn)
Terminal pitch 0.5 mm - - 0.95 mm 0.65 mm 0.95 mm
Maximum time at peak reflow temperature NOT SPECIFIED - - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 1 mm - - 1.6 mm 1.25 mm 1.6 mm

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