W24010/LL
128K
×
8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W24010 is a normal-speed, very low-power CMOS static RAM organized as 131072
×
8 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
•
•
•
•
•
•
Low power consumption:
−
Active: 350 mW (max.)
−
Standby: 250
µW
(max.)
Access time: 70 nS (max.)
Single 5V power supply
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
•
•
•
Battery back-up operation capability
Data retention voltage: 2V (min.)
Packaged in 32-pin 600 mil DIP, 450 mil SOP,
standard type one TSOP (8 mm
×
20 mm),
reverse type one TSOP (8 mm
×
20 mm),
small type one TSOP (8 mm
×
13.4 mm) and
reverse small type one TSOP (8 mm
×
13.4
mm)
PIN CONFIGURATIONS
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
BLOCK DIAGRAM
CLK GEN.
A16
A14
A12
A4
A3
A2
A7
A6
A5
A9
I/O1
:
I/O8
DATA
CNTRL.
CLK
GEN.
WE
CS1
CS2
OE
A15
A13
A8 A1 A0 A11 A10
I/O CKT.
COLUMN DECODER
R
O
W
D
E
C
O
D
E
R
PRECHARGE CKT.
CORE CELL ARRAY
1024 ROWS
128 X 8 COLUMNS
A11
A9
A8
A13
WE
CS2
A15
V
DD
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin
TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
V
SS
I/O3
I/O2
I/O1
A0
A1
A2
A3
PIN DESCRIPTION
SYMBOL
A0−A16
I/O1−I/O8
CS1, CS2
WE
OE
V
DD
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Input
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
A4
A5
A6
A7
A12
A14
A16
NC
V
DD
A15
CS2
WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
32-pin
Reverse
TSOP
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
I/O1
I/O2
I/O3
V
SS
I/O4
I/O5
I/O6
I/O7
I/O8
CS1
A10
OE
-1-
Publication Release Date: April 1997
Revision A3
W24010/LL
TRUTH TABLE
CS1
H
X
L
L
L
CS2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
MODE
Not Selected
Not Selected
Output Disable
Read
Write
I/O1−I/O8
High Z
High Z
High Z
Data Out
Data In
V
DD
CURRENT
I
SB
, I
SB1
I
SB
, I
SB1
I
DD
I
DD
I
DD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
Supply Voltage to V
SS
Potential
Input/Output to V
SS
Potential
Allowable Power Dissipation
Storage Temperature
Operating Temperature
RATING
-0.5 to +7.0
-0.5 to V
DD
+0.5
1.0
-65 to +150
0 to 70
UNIT
V
V
W
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Operating Characteristics
(V
DD
= 5V
±10%;
V
SS
= 0V; T
A
= 0° C to 70° C)
PARAMETER
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage
Current
SYM.
V
IL
V
IH
I
LI
I
LO
TEST CONDITIONS
-
-
V
IN
= V
SS
to V
DD
V
I/O
= V
SS
to V
DD,
CS = V
IH
(min.) or OE = V
IH
(min.) or
WE = V
IL
(max.)
I
OL
= +2.1 mA
I
OH
= -1.0 mA
CS = V
IL
(max.), I/O = 0 mA,
Cycle = min. Duty = 100%
CS = V
IH
(min.), Cycle =
min. Duty = 100%
CS
≥
V
DD
-0.2V
MIN.
-0.5
+2.2
-1
-1
TYP.
-
-
-
-
MAX.
+0.8
V
DD
+0.5
+1
+1
UNIT
V
V
µA
µA
Output Low Voltage
Output High Voltage
Operating Power
Supply Current
Standby Power
Supply Current
V
OL
V
OH
I
DD
I
SB
I
SB1
-
2.4
-
-
-
-
-
-
-
-
0.4
-
70
3
50
V
V
mA
mA
µA
-2-
W24010/LL
CAPACITANCE
(V
DD
= 5V, T
A
= 25° C, f = 1 MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYM.
C
IN
C
I/O
CONDITIONS
V
IN
= 0V
V
OUT
= 0V
MAX.
6
8
UNIT
pF
pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
0V to 3.0V
5 nS
1.5V
See the drawing below
CONDITIONS
AC Test Loads and Waveform
1 TTL
OUTPUT
100 pF
Including
Jig and
Scope
OUTPUT
1 TTL
5 pF
Including
Jig and
Scope
(For T
CLZ,
T
OLZ,
T
CHZ,
T
OHZ,
T
WHZ,
T
OW
)
3.0V
0V
5 nS
90%
10%
90%
10%
5 nS
-3-
Publication Release Date: April 1997
Revision A3
W24010/LL
AC Characteristics, continued
(V
DD
= 5V
±10%;
V
SS
= 0V; T
A
= 0° C to 70° C)
Read Cycle
PARAMETER
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
∗These
parameters are sampled but not 100% tested
SYMBOL
T
RC
T
AA
T
ACS
T
AOE
T
CLZ
*
T
OLZ
*
T
CHZ
*
T
OHZ
*
T
OH
MIN.
70
-
-
-
10
5
-
-
10
MAX.
-
70
70
35
-
-
30
30
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
Write Cycle
PARAMETER
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
Output Disable to Output in High Z
Output Active from End of Write
∗
These parameters are sampled but not 100% tested
CS1
, CS2, WE
SYMBOL
T
WC
T
CW
T
AW
T
AS
T
WP
T
WR
T
DW
T
DH
T
WHZ
*
T
OHZ
*
T
OW
MIN.
70
50
50
0
50
0
30
0
-
-
5
MAX.
-
-
-
-
-
-
-
-
25
25
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
-4-
W24010/LL
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
T
RC
Address
T
OH
D
OUT
T
AA
T
OH
Read Cycle 2
(Chip Select Controlled)
CS1
CS2
T
ACS
T
CLZ
D
OUT
T
CHZ
Read Cycle 3
(Output Enable Controlled)
T
RC
Address
T
AA
OE
T
AOE
T
OLZ
CS1
CS2
T
OH
T
ACS
D
OUT
T
CLZ
T
CHZ
T
OHZ
-5-
Publication Release Date: April 1997
Revision A3