Philips Semiconductors
Product specification
Quad buffer/line driver with 5 Volt tolerant input/outputs;
3-state
FEATURES
•
5 V tolerant inputs/outputs for interfacing with 5 V logic
•
Wide supply voltage range from 1.2 to 3.6 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Inputs accept voltages up to 5.5 V
•
Complies with JEDEC standard no. 8-1A
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
DESCRIPTION
74LVC125A
The 74LVC125A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V.
The 74LVC125A consists of four non-inverting buffers/line
drivers with 3-state outputs (nY) which are controlled by
the output enable input (nOE). A HIGH at nOE causes the
outputs to assume a high-impedance OFF-state.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
TEMPERATURE RANGE
74LVC125AD
74LVC125ADB
74LVC125APW
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
PINS
14
14
14
PACKAGE
SO
SSOP
TSSOP
MATERIAL
plastic
plastic
plastic
CODE
SOT108-1
SOT337-1
SOT402-1
PARAMETER
propagation delay nA to nY
input capacitance
power dissipation capacitance per gate
V
CC
= 3.3 V;
notes 1 and 2
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
TYPICAL
2.4
4.0
12
ns
pF
pF
UNIT
2002 Mar 08
2
Philips Semiconductors
Product specification
Quad buffer/line driver with 5 Volt tolerant input/outputs;
3-state
FUNCTION TABLE
See note 1.
INPUTS
nOE
L
L
H
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
PINNING
PIN
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
7
14
1OE to 4OE
1A to 4A
1Y to 4Y
GND
V
CC
SYMBOL
data input
data output
ground (0 V)
supply voltage
nA
L
H
X
74LVC125A
OUTPUTS
nY
L
H
Z
DESCRIPTION
data enable input (active LOW)
handbook, halfpage
2
1OE
1A
1Y
2OE
2A
2Y
GND
1
2
3
4
5
6
7
MNA226
1A
1OE
2A
2OE
3A
3OE
4A
4OE
1Y
3
14 VCC
13 4OE
12 4A
1
5
4
2Y
6
125
11 4Y
9
10 3OE
9
3A
10
12
13
3Y
8
8 3Y
4Y
11
MNA228
Fig.1 Pin configuration.
Fig.2 Logic symbol.
2002 Mar 08
3
Philips Semiconductors
Product specification
Quad buffer/line driver with 5 Volt tolerant input/outputs;
3-state
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
t
r
, t
f
PARAMETER
supply voltage
input voltage
output voltage
operating ambient temperature
input rise and fall times
V
CC
= 1.2 to 2.7 V
V
CC
= 2.7 to 3.6 V
output HIGH or LOW state
output 3-state
CONDITIONS
for maximum speed performance
for low voltage applications
MIN.
2.7
1.2
0
0
0
−40
0
0
74LVC125A
MAX.
3.6
3.6
5.5
V
CC
5.5
+125
20
10
V
V
V
V
V
UNIT
°C
ns/V
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
tot
PARAMETER
supply voltage
input diode current
input voltage
output diode current
output voltage
output source or sink current
V
CC
or GND current
storage temperature
power dissipation per package
SO package
SSOP and TSSOP packages
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
above 70
°C
derate linearly with
8 mW/K
above 60
°C
derate linearly with
5.5 mW/K
−
−
500
500
mW
mW
V
I
< 0
note 1
V
O
> V
CC
or V
O
< 0
output HIGH or LOW state; note 1
output 3-state; note 1
V
O
= 0 to V
CC
CONDITIONS
−
−0.5
−
−0.5
−0.5
−
−
−65
MIN.
−0.5
MAX.
+6.5
−50
+6.5
±50
+6.5
±50
±100
+150
V
mA
V
mA
V
mA
mA
°C
UNIT
V
CC
+ 0.5 V
2002 Mar 08
5
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