Integrated
Circuit
Systems, Inc.
Product Data Sheet
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
MR_SEL3
GND
NC
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
MR_SEL2
MR_SEL0
MR_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
G
ENERAL
D
ESCRIPTION
The M1025/26 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1025/26 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
◆
Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
◆
Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
◆
LVPECL clock output (CML and LVDS options available)
◆
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆
Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
◆
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
◆
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
◆
Hitless Switching (HS) options with or without Phase
Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
◆
Pin-selectable feedback and reference divider ratios
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
28
29
30
31
32
33
34
35
36
M1025
M1026
(Top View)
18
17
16
15
14
13
12
11
10
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
F
EATURES
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using
M1025-11-155.5200 or M1026-11-155.5200
Input Reference
Clock (MHz)
(M1025)
(M1026)
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
PLL Ratio
(Pin Selectable)
(M1025)
(M1026)
Output Clock
(MHz)
(Pin Selectable)
19.44 or 38.88
77.76
155.52
622.08
8 or 4
2
1
0.25
155.52
or
77.76
Table 1: Example I/O Clock Frequency Combinations
S
IMPLIFIED
B
LOCK
D
IAGRAM
M1025/26
NBW
MUX
PLL
Phase
Detector
Loop Filter
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
Auto
Ref Sel
0
R Div
VCSO
1
0
1
M Divider
LOL
Phase
Detector
LOL
FOUT
nFOUT
MR_SEL3:0
4
M/R
Divider
LUT
P Divider
(1, 2, or TriState)
TriState
P_SEL1:0
2
P Divider
LUT
Figure 2: Simplified Block Diagram
M1025/26 Datasheet Rev 1.0
M1025/26 VCSO Based Clock PLL with AutoSwitch
Revised 28Jul2004
●
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
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M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Product Data Sheet
P
IN
D
ESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
4
9
5
8
6
7
11, 19, 33
12
Name
GND
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
AUTO
I/O
Configuration
Description
Ground
Input
Output
Input
Power
Input
Power supply ground connections.
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 9.
Power supply connection, connect to +
3.3
V.
Automatic/manual reselection mode for clock input:
Internal pull-down resistor
1
Logic
1
automatic reselection upon clock failure
(non-revertive)
Logic
0
manual selection only (using
REF_SEL
)
Reference Acknowledgement pin for input mux state; outputs
the currently selected reference input pair:
Logic
1
indicates
nDIF_REF1, DIF_REF1
Logic
0
indicates
nDIF_REF0, DIF_REF0
No internal terminator
Clock output pair. Differential LVPECL (CML, LVDS available).
13
15
16
17
18
20
21
22
23
24
25
27
28
29
30
31
REF_ACK
FOUT
nFOUT
P_SEL1
P_SEL0
nDIF_REF1
DIF_REF1
REF_SEL
nDIF_REF0
DIF_REF0
NC
MR_SEL3
MR_SEL2
MR_SEL0
MR_SEL1
LOL
Output
Output
, P divider selection. LVCMOS/LVTTL. See Table 5,
Internal pull-down resistor
1
Post-PLL Look-Up Table (LUT), on pg. 4.
P Divider
Input
Input
Input
Reference clock input pair 1. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
Internal pull-down resistor
1
Reference clock input selection. LVCMOS/LVTTL:
Internal pull-down resistor
1
Logic
1
selects
DIF_REF1, nDIF_REF1.
Logic
0
selects
DIF_REF0, nDIF_REF0
.
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
Internal pull-down resistor
1
No internal connection.
Internal pull-down resistor
1
Biased to Vcc/2
2
Biased to Vcc/2
2
Input
M and R divider value selection. LVCMOS/ LVTTL.
See Tables 3 and 4, M and R Divider Look-Up Tables (LUT)
on pg. 3.
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase.
3
Logic
1
indicates loss of lock.
Logic
0
indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic
1
- Narrow loop bandwidth
, R
IN
= 2100kΩ
.
Logic
0
- Wide bandwidth
, R
IN
= 100kΩ
.
Table 2: Pin Descriptions
Output
32
34, 35, 36
NBW
DNC
Input
Internal pull-UP resistor
1
Do Not Connect.
Note 1: For typical values of internal pull-down and pull-UP resistors, see
DC Characteristics
on pg. 11.
Note 2: Biased toVcc/2, with 50kΩ to Vcc and 50kΩ to ground. See
Differential Inputs Biased to VCC/2
on pg. 11.
Note 3: See
LVCMOS Output
in
DC Characteristics
on pg. 11.
M1025/26 Datasheet Rev 1.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
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Systems, Inc.
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Product Data Sheet
D
ETAILED
B
LOCK
D
IAGRAM
R
LOOP
C
LO OP
R
POST
C
PO ST
C
PO ST
R
LOOP
C
LO OP
OP_OUT
R
POST
nOP_OUT
nVC
VC
External
Loop Filter
Components
M1025/26
OP_IN
nOP_IN
Hitless Switching (HS) Opt.
NBW
M UX
PLL
Phase
Detector
HS with Phase Build-out O pt.
R
IN
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
Auto
Ref Sel
0
R Div
R
IN
Loop Filter
Am plifier
1
Phase
Locked
Loop
(PLL)
SAW Delay Line
Phase
Shifter
VCSO
0
1
M Divider
LOL
Phase
Detector
LO L
M / R Divider
LUT
M R_SEL3:0
4
(1, 2, or TriState)
P Divider
TriState
FO UT
nFO UT
P_SEL1:0
2
P Divider
LUT
Figure 3: Detailed Block Diagram
D
IVIDER
S
ELECTION
T
ABLES
M and R Divider Look-Up Tables (LUT)
The
MR_SEL3:0
pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up tables vary
by device variant. M1025 and M1026 are defined in
Tables 3 and 4 respectively.
M1025 M/R Divider LUT
Phase Det.
Total
Fin for
Freq. for
MR_SEL3:0
M Div R Div PLL
155.52MHz
155.52MHz
Ratio VCSO (MHz)
VCSO (MHz)
ables 3 and 4 provide example Fin and phase
detector frequencies with
155.52MHz
VCSO
devices (M1025-11-155.5200 and
M1026-11-155.5200).
See “Ordering Information” on pg. 14.
M1026 M/R Divider LUT
Phase Det.
Total
Fin for
Freq. for
MR_SEL3:0
M Div R Div PLL
155.52MHz
155.52MHz
Ratio VCSO (MHz)
VCSO (MHz)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
8
32
128
512
2
8
32
128
1
4
16
64
1
4
16
1
4
16
64
1
4
16
64
1
4
16
64
4
16
64
8
8
8
8
2
2
2
2
1
1
1
1
N/A
0.25
0.25
0.25
19.44
19.44
19.44
19.44
77.76
77.76
77.76
77.76
155.52
155.52
155.52
155.52
N/A
622.08
622.08
622.08
19.44
4.86
1.215
0.30375
77.76
19.44
4.86
1.215
155.52
38.88
9.72
2.43
N/A
155.52
38.88
9.72
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4
16
64
256
2
8
32
128
1
4
16
64
1
4
16
1
4
16
64
1
4
16
64
1
4
16
64
4
16
64
4
4
4
4
2
2
2
2
1
1
1
1
N/A
0.25
0.25
0.25
38.88
38.88
38.88
38.88
77.76
77.76
77.76
77.76
155.52
155.52
155.52
155.52
N/A
622.08
622.08
622.08
38.88
9.72
2.43
0.6075
77.76
19.44
4.86
1.215
155.52
38.88
9.72
2.43
N/A
155.52
38.88
9.72
Test Mode
1
Test Mode
1
Table 3: M1025 M/R Divider LUT
Table 4: M1026 M/R Divider LUT
Note 1: Factory test mode; do not use.
Note 1: Factory test mode; do not use.
M1025/26 Datasheet Rev 1.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
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Systems, Inc.
General Guidelines for M and R Divider Selection
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Product Data Sheet
General guidelines for M/R divider selection (see
following pages for more detail):
F
UNCTIONAL
D
ESCRIPTION
The M1025/26 is a PLL (Phase Locked Loop) based
clock generator that generates an output clock synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW delay line provides low jitter
signal performance.
A pin-selected look-up table is used to select the PLL
feedback divider (M Div) and reference divider (R Div)
as shown in
Tables 3 and 4 on pg. 3.
These look-up
tables provide flexibility in both the overall frequency
multiplication ratio (total PLL ratio) and phase detector
frequency.
The M1025/26 includes a Loss of Lock (
LOL
) indicator,
which provides status information to system
management software. A Narrow Bandwidth (
NBW
)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
An automatic input reselection feature, or “AutoSwitch”
is also included in the M1025/26. When the AutoSwitch
mode is enabled, the device will automatically switch to
the other reference clock input when the currently
selected reference clock fails. Reference selection is
non-revertive, meaning that only one reference
reselection will be made each time that AutoSwitch is
re-enabled.
In addition to the AutoSwitch feature, Hitless Switching
and Phase Build-out options can be ordered with the
device. The Hitless Switching and Phase Build-out
options help assure SONET/SDH MTIE and TDEV
compliance during either a manual or automatic input
reference reselection.
•
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is
19.44MHz
. The LOL pin should
not be used during loop timing mode.
When
LOL
is to be used for system health monitoring,
the phase detector frequency should be
5MHz
or
greater. Low phase detector frequencies make
LOL
overly sensitive, and higher phase detector
frequencies make
LOL
less sensitive.
The preceding guideline also applies when using the
AutoSwitch Mode, since AutoSwitch uses
the
LOL
output for clock fault detection.
•
•
P Divider Look-Up Table (LUT)
The
P_SEL1
and
P_SEL0
pins select the post-PLL divider
value P. The output frequency of the SAW can be
divided by
1
or
2
or the output can be TriStated as
specified in Table 5.
P_SEL1:0
P Value
2
1
2
TriState
M1025-155.5200 or M1026-155.5200
0
0
1
1
0
1
0
1
Output Frequency (MHz)
77.76
155.52
77.76
N/A
Table 5: P Divider Look-Up Table (LUT)
M1025/26 Datasheet Rev 1.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
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Integrated
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Systems, Inc.
Input Reference Clocks
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Product Data Sheet
PLL Operation
The M1025/26 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
The “M” divider divides the VCSO output frequency,
feeding the result into the plus input of the phase
detector. The output of the “R” divider is fed into the
minus input of the phase detector. The phase detector
compares its two inputs. The phase detector output,
filtered externally, causes the VCSO to increase or
decrease in speed as needed to phase- and
frequency-lock the VCSO to the reference input.
The value of the M divider directly affects closed loop
bandwidth.
Implementation of single-ended input has been
facilitated by biasing
nDIF_REF0
and
nDEF_REF1
to Vcc/2,
with 50kΩ to Vcc and 50kΩ to ground. Figure 4 shows
the input clock structure and how it is used with either
LVCMOS / LVTTL inputs or a DC- coupled LVPECL
clock.
DIF_REF0
50k
Ω
VCC
50k
Ω
X
50k
Ω
MUX
LVCMOS/
LVTTL
nDIF_REF0
VCC
0
DIF_REF1
LVPECL
127
Ω
VCC
127
Ω
VCC
50k
Ω
1
The relationship between the nominal VCSO center
frequency (Fvcso), the M divider, the R divider, and the
input reference frequency (Fin) is:
M
-
Fvcso
=
Fin
×
---
R
For the available M divider and R divider look-up table
combinations,
Tables 3 and 4 on pg. 3
list the Total PLL
Ratio as well as Fin when using the
M1025-11-155.5200
or
the
M1026-11-155.5200
.
(“Ordering Information”, pg. 14.)
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
Post-PLL Divider
82
Ω
50k
Ω
nDIF_REF1
REF_SEL
82
Ω
50k
Ω
M1025/26
Figure 4: Input Reference Clocks
The M1025/26 features a post-PLL (P) divider. By using
the P Divider, the device’s output frequency (Fout) can
be the VCSO center frequency (Fvcso) or 1/2 Fvcso.
The
P_SEL
pin selects the value for the P divider: logic
1
sets P to
2,
logic
0
sets P to
1
. (See Table 5 on pg. 4.)
When the P divider is included, the complete relation-
ship for the output frequency (Fout) is defined as:
M
Fvcso
-
Fout
=
-------------------
=
Fin
×
-----------------
P
Differential LVPECL Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the
127Ω
and
82Ω
resistors) will work for both AC and DC
coupled LVPECL reference clock lines. These provide
the
50Ω
load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(
DIF_REF0
or
DIF_REF1
). The inverting reference input pin
(
nDIF_REF0
or
nDIF_REF1
) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or
nDEF_REF1)
is left floating (not
connected), the input will self-bias at VCC/2.
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
R
×
P
M1025/26 Datasheet Rev 1.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
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Revised 28Jul2004
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