Product Brief
February 2006
ET2005-50
Gigabit Ethernet Five-Port Switch and PHY
802.1d STP and 802.1w Rapid STP
Broadcast storm control
One externally exposed MII/GMII/RGMII interface (to
allow for switch-to-switch connections)
ET2
005
-50
Direct-drive/serial LEDs and on-chip LED drivers
NOR flash interface for boot code
EEPROM interface for configuration
CPU peripheral support:
— UART
— GPIO x 5
Features
Web-managed switch controller with five integrated
10/100/1000 Mbits/s Ethernet PHY ports
Embedded
ARM
®
7TDMI processor:
— 8-Kbytes unified cache and 128-Kbytes internal
SRAM
— Expandable up to 4-Mbytes through the addition of an
external SRAM
Wire-speed and nonblocking performance
Hardware-based learning, aging, and forwarding
Layer 2/3/4 ACL support
Integrated 4K MAC address table
QoS for egress traffic:
— Four priority queues per port
Ingress classification based on 802.1p, IPv4 TOS, DSCP,
IPv6, or DMAC
Extensive VLAN support:
— Up to 128 simultaneous VLANs
— Port-based VLANs
— Protocol-based VLANs
— Private VLANs
Integrated 1.25 Mbit packet buffer
9-Kbytes jumbo packet
RMON counters (full Ethernet statistics)
IGMP snooping
802.1x MAC authentication
388-PBGA package
Total power consumption < 4.3 W
Standards supported:
—
IEEE
®
802.3u, 802.3z, and 802.3ab
—
IEEE
802.1d
—
IEEE
802.1p
—
IEEE
802.1q
—
IEEE
802.3x
—
IEEE
802.1x port-based and MAC-based
—
IEEE
802.3ad link aggregation
TruePHY™
cable diagnostics
2.5 V and 1.1 V power supplies
Description
The ET2005-50 is a five-port gigabit Ethernet switch and
PHY fabricated on a single CMOS chip. Packaged in a
388-pin PBGA, the ET2005-50 is built on 0.13 µm technol-
ogy for low-power consumption. Its primary target market is
the small-office/home-office (SOHO) switch space. The
integrated 10/100/1000Base-T octal PHY is fully compliant
with
IEEE
802.3u, 802.3z, and 802.3ab standards.
The ET2005-50 provides an embedded
ARM-7
processor
for web-based network management. Integrated access
control lists (ACLs) enable advanced network security at
the edge of the network. ACLs enable the user to selec-
tively permit or deny access to the network. Additionally,
advanced quality-of-service features within the ET2005-50
support converged voice, data, and video applications with-
out sacrificing network performance.
Agere Systems - Proprietary
ET2005-50
Gigabit Ethernet Five-Port Switch and PHY
Product Brief
February 2006
PHY Overview
Agere Systems’ ET2005-50 incorporates a high-performance Layer-2 Ethernet switching controller with five
10/100/1000 Mbits/s integrated PHYs and an embedded
ARM7
CPU. Figure 1 is a block diagram of its basic con-
figuration. Figure 2 shows a block diagram of the switch.
OR Flash
Interface
GMII_0
MII/GMII/RGMI
I
8-Bit/Interface
Addressable to 4 MB
TCK
TRST_N
TMS
TDI
TDO
LED_A/B_[0:7]
LED_SER
ARM7
CPU
ARM7
CPU
JTAG/
Test
Management
Interface
MDINT_N
MDC
MDIO
XTAL_0
XTAL_1 / CLKIN
RESET_N
5-Port Switch
8-Port Switch
Clock
LEDS/ Config/
LED Serial
Reset / POR
PHY Port 0
PHY Port 4
PHY Port 7
TRD_0_[0:3]+/-
AFE
PHY Digital
GMII
GMII
PHY Digital
AFE
4
TRD_7_[0:3]+/-
PHY Port 1
PHY Port
PHY Port 3
6
GMII
GMII
PHY Digital
AFE
TRD_1_[0:3]+/-
AFE
PHY Digital
3
TRD_6_[0:3]+/-
PHY Port 2
PHY Port 5
GMII
GMII
PHY Digital
AFE
TRD_2_[0:3]+/-
AFE
PHY Digital
TRD_5_[0:3]+/-
PHY Port 3
PHY Port 4
Figure 1. ET2005-50 Block Diagram
2
Agere Systems - Proprietary
Agere Systems Inc.
Product Brief
February 2006
ET2005-50
Gigabit Ethernet Five-Port Switch and PHY
Five-Port GbE Switch Overview
The ET2005-50 switch controller is composed of four basic functional blocks, including a switching core module
(SCM), an address lookup engine (ALE), five port-controller modules (PCM), and an embedded CPU.
The SCM stores incoming packets in an internal synchronous SRAM, and builds the switching paths to send out
packets in a nonblocking manner.
The ALE uses four-way set-associative address lookup for Layer 2 switching. Embedded 4K entries of the
address lookup table (ALT) are provided to store MAC addresses for the learning database.
The PCM includes multiple-speed Ethernet MAC controllers and statistic counters.
The embedded
ARM7,
with 8 Kbyte unified cache and 128 Kbyte SRAM, processes the packet for network pro-
tocol implementation using only big-endian support.
UART
GPIO
DMA
Buffer
Memory
PCM0
ARM
ARM7
Mem I/F
SRAM
Cache
VLAN
Table
Switch Engine (SCM)
PCM1
PCM5
PCM7
AN
Lookup
Engine
(ALE)
Address
Table
Figure 2. ET2005-50 Switch Block Diagram
A data packet entering the ET2005-50 controller is first processed by the PCM and is then passed to the SCM for
temporary storage; meanwhile, the address field is sent to the ALE for switching resolution. When the output
port(s) and address(es) are identified, the packet is retrieved from storage and then passed to the outgoing
PCM(s) for transmission, or to the CPU for further processing.
Agere Systems Inc.
Agere Systems - Proprietary
3
ET2005-50
Gigabit Ethernet Five-Port Switch and PHY
Product Brief
February 2006
Ordering Information
Table 1. Ordering Information
Device
ET2005-50
ET2005-50
Description
Gigabit Ethernet Five-Port Switch and PHY
Lead-Free Gigabit Ethernet Five-Port Switch and PHY
Part Number
TBD
TBD
Comcode
TBD
TBD
Related Documentation
Table 2. Related Documentation
Device
ET1011
ET1310
ET1081
ET2008-30
ET2008-40
ET2008-50
ET2005-30
ET2005-40
ET3028-50
ET3048-50
ET4028-50
ET4048-50
ET4128-50
ET4148-50
ET5148-50
Gigabit Ethernet Transceiver
Gigabit Ethernet Controller
Gigabit Ethernet Octal PHY
Gigabit Ethernet Octal Switch and PHY
Gigabit Ethernet Octal Switch and PHY
Gigabit Ethernet Octal Switch and PHY
Gigabit Ethernet Five-Port Switch and PHY
Gigabit Ethernet Five-Port Switch and PHY
Single-Chip 28 x 1 Gbit/s Layer 2 Ethernet Switch
Single-Chip 48 x 1 Gbit/s Layer 2 Ethernet Switch
Single-Chip 28 x 1 Gbit/s Layer 2+ Ethernet Switch
Single-Chip 48 x 1 Gbit/s Layer 2+ Ethernet Switch
Single-Chip 28 x 1 Gbit/s + 2x 10 Gbits/s Layer 2+ Ethernet Switch
Single-Chip 48 x 1 Gbit/s + 2x 10 Gbits/s Layer 2+ Ethernet Switch
Single-Chip 48 x 1 Gbit/s + 2x 10 Gbits/s Layer 2/3 Ethernet Switch
Product Brief
Product Brief
Data Sheet
Application Note
Description
Document Type
Product Brief
Data Sheet
Application Note
Product Brief
Data Sheet
Product Brief
IEEE
is a registered trademark of the Institute of Electrical and Electronics Engineers, Inc.
ARM
is a registered trademark of ARM Limited.
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
Home:
http://www.agere.com
Sales:
http://www.agere.com/sales
E-MAIL:
docmaster@agere.com
N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138
1-800-372-2447,
FAX 610-712-4106 (In CANADA:
1-800-553-2448,
FAX 610-712-4106)
ASIA:
CHINA:
(86) 21-54614688
(Shanghai),
(86) 755-25881122
(Shenzhen),
(86) 10-65391096
(Beijing)
JAPAN:
(81) 3-5421-1600
(Tokyo), KOREA:
(82) 2-767-1850
(Seoul), SINGAPORE:
(65) 6741-9855,
TAIWAN:
(886) 2-2725-5858
(Taipei)
EUROPE:
Tel. (44) 1344 296 400
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Agere, Agere Systems, and the Agere logo are registered trademarks of Agere Systems Inc.
TruePHY
is a trademark of Agere Systems.
Copyright © 2006 Agere Systems Inc.
All Rights Reserved
February 2006
PB06-025GSWC
Agere Systems - Proprietary
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