GTL2107
12-bit GTL−/GTL/GTL+ to LVTTL translator
Rev. 05 — 23 December 2009
Product data sheet
1. General description
The GTL2107 is a customized translator between dual Xeon processors, GTL−/GTL/GTL+
I/O and the Platform Health Management, South Bridge and Power Supply 3.3 V LVTTL
and GTL signals.
2. Features
Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver
Operates at GTL, GTL+ or GTL− levels
EN1 and EN2 enable control
3.0 V to 3.6 V operation
LVTTL I/O not 5 V tolerant
Series termination on the LVTTL outputs of 30
Ω
ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 Class II, Level A which exceeds
500 mA
Package offered: TSSOP28
3. Quick reference data
Table 1.
Quick reference data
T
amb
= 25
°
C.
Symbol
t
PLH
t
PHL
Parameter
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
Conditions
nA to nBI; see
Figure 4
nBI to nA or nAO (open-drain outputs); see
Figure 13
nA to nBI; see
Figure 4
nBI to nA or nAO (open-drain outputs); see
Figure 13
nA to nBI; see
Figure 4
nBI to nA or nAO (open-drain outputs); see
Figure 13
nA to nBI; see
Figure 4
nBI to nA or nAO (open-drain outputs); see
Figure 13
Min
1
2
2
2
1
2
2
2
Typ
4
13
5.5
4
4
13
5.5
4
Max
8
18
10
10
8
18
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
ref
= 0.73 V; V
TT
= 1.1 V
V
ref
= 0.76 V; V
TT
= 1.2 V
t
PLH
t
PHL
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
NXP Semiconductors
GTL2107
12-bit GTL−/GTL/GTL+ to LVTTL translator
4. Ordering information
Table 2.
Ordering information
T
amb
=
−
40
°
C to +85
°
C.
Type
number
Topside
mark
Package
Name
TSSOP28
Description
plastic thin shrink small outline package; 28 leads; body width 4.4 mm
Version
SOT361-1
GTL2107PW GTL2107
5. Functional diagram
GTL2107
GTL VREF
1AO
LVTTL outputs
(open-drain)
2AO
1
2
27
1BI
GTL inputs
3
26
2BI
5A
LVTTL inputs/outputs
(open-drain)
6A
LVTTL input
EN1
4
&
25
7BO1
GTL outputs
5
6
&
24
7BO2
23
7
EN2
LVTTL input
GTL input
11BI
1
22
11BO
GTL output
LVTTL input/output
(open-drain)
11A
8
DELAY
(1)
21
5BI
GTL input
9BI
9
DELAY
(1)
20
6BI
GTL inputs
3AO
LVTTL outputs
(open-drain)
4AO
10
19
3BI
11
18
4BI
1
10AI1
LVTTL inputs
10AI2
13
12
1
17
10BO1
GTL outputs
16
10BO2
15
9AO
LVTTL output
002aac745
(1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition (where 5BI/6BI go from LOW to HIGH, and the
LOW to HIGH on 5A/6A lags up to 100 ns) from causing a LOW glitch on the 7BO1/7BO2 outputs.
Fig 1.
GTL2107_5
Logic diagram of GTL2107
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 23 December 2009
2 of 19
NXP Semiconductors
GTL2107
12-bit GTL−/GTL/GTL+ to LVTTL translator
6. Pinning information
6.1 Pinning
VREF
1AO
2AO
5A
6A
EN1
11BI
11A
9BI
1
2
3
4
5
6
7
8
9
28 V
CC
27 1BI
26 2BI
25 7BO1
24 7BO2
23 EN2
22 11BO
21 5BI
20 6BI
19 3BI
18 4BI
17 10BO1
16 10BO2
15 9AO
002aac746
GTL2107PW
3AO 10
4AO 11
10AI1 12
10AI2 13
GND 14
Fig 2.
Pin configuration for TSSOP28
6.2 Pin description
Table 3.
Symbol
VREF
1AO
2AO
5A
6A
EN1
11BI
11A
9BI
3AO
4AO
10AI1
10AI2
GND
9AO
10BO2
10BO1
4BI
3BI
GTL2107_5
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Description
GTL reference voltage
data output (LVTTL), open-drain
data output (LVTTL), open-drain
data input/output (LVTTL), open-drain
data input/output (LVTTL), open-drain
enable input (LVTTL)
data input (GTL)
data input/output (LVTTL), open-drain
data input (GTL)
data output (LVTTL), open-drain
data output (LVTTL), open-drain
data input (LVTTL)
data input (LVTTL)
ground (0 V)
data output (LVTTL), push-pull
data output (GTL)
data output (GTL)
data input (GTL)
data input (GTL)
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 23 December 2009
3 of 19
NXP Semiconductors
GTL2107
12-bit GTL−/GTL/GTL+ to LVTTL translator
Pin description
…continued
Pin
20
21
22
23
24
25
26
27
28
Description
data input (GTL)
data input (GTL)
data output (GTL)
enable input (LVTTL)
data output (GTL)
data output (GTL)
data input (GTL)
data input (GTL)
positive supply voltage
Table 3.
Symbol
6BI
5BI
11BO
EN2
7BO2
7BO1
2BI
1BI
V
CC
7. Functional description
Refer to
Figure 1 “Logic diagram of GTL2107”.
7.1 Function tables
Table 4.
Power supervisor power good control
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
Inputs
EN1
H
H
L
1BI/2BI
L
H
X
Output
1AO/2AO (open-drain)
L
H
H
Table 5.
Power supervisor power good control
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
Inputs
EN2
H
H
L
3BI/4BI
L
H
X
Output
3AO/4AO (open-drain)
L
H
H
Table 6.
Southbridge SMI_L control
H = HIGH voltage level; L = LOW voltage level.
Input
9BI
L
H
Output
9AO (push-pull)
L
H
GTL2107_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 23 December 2009
4 of 19
NXP Semiconductors
GTL2107
12-bit GTL−/GTL/GTL+ to LVTTL translator
Table 7.
CPU SMI_L control
H = HIGH voltage level; L = LOW voltage level.
Inputs
10AI1/10AI2
L
L
H
H
9BI
L
H
L
H
Output
10BO1/10BO2
L
L
L
H
Table 8.
PROCHOT L control
H = HIGH voltage level; L = LOW voltage level.
Inputs
EN2
H
H
H
L
L
L
L
[1]
Input/output
5BI/6BI
L
H
H
H
H
L
L
5A/6A (open-drain)
L
L
[2]
H
L
[2]
H
H
L
[2]
Output
7BO1/7BO2
H
[1]
L
H
L
H
H
H
The enable on 7BO1/7BO2 includes a delay that prevents the transient condition (where 5BI/6BI goes from
LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns) from causing a low glitch on the
7BO1/7BO2 outputs.
Open-drain input/output terminal is driven to logic LOW state by an external driver.
[2]
Table 9.
Southbridge NMI control
H = HIGH voltage level; L = LOW voltage level.
Input
11BI
L
L
H
[1]
Input/output
11A (open-drain)
H
L
[1]
L
Output
11BO
L
H
H
Open-drain input/output terminal is driven to logic LOW state by an external driver.
GTL2107_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 23 December 2009
5 of 19
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