Approved Product
C9832H
High Performance Pentium® 4 Clock Synthesizer
Product Features
•
•
•
Supports Pentium 4 type CPUs
3.3 Volt Power supply
10 copies of PCI clocks
®
•
•
•
•
•
•
3 differential CPU clocks
SMBus Support with read back capabilities
Spread Spectrum EMI Reduction
Dial-a-Frequency™ features
Dial-a-dB™ features
56 Pin SSOP and TSSOP package
Frequency Table
S2
1
1
1
1
0
0
0
0
M
M
S1
0
0
1
1
0
0
1
1
0
0
S0
0
1
0
1
0
1
0
1
0
1
CPU
(0:2)
66M
100M
200M
133M
66M
100M
200M
133M
Hi-Z
TCLK/2
3V66
66M
66M
66M
66M
66M
66M
66M
66M
Hi-Z
TCLK/4
66BUFF(0:2)/
3V66(0:4)
66IN
66IN
66IN
66IN
66M
66M
66M
66M
Hi-Z
TCLK/4
66IN/
3V66-5
66MHz clock input
66MHz clock input
66MHz clock input
66MHZ clock input
66M
66M
66M
66M
Hi-Z
TCLK/4
PCI_F
PCI
66IN/2
66IN/2
66IN/2
66IN/2
33 M
33 M
33 M
33 M
Hi-Z
TCLK/8
REF
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
Hi-Z
TCLK
USB/
DOT
48M
48M
48M
48M
48M
48M
48M
48M
Hi-Z
TCLK/2
Note:
TCLK is a test clock over driven on the XTAL_IN input during test mode. M= driven to a level between 1.0 and 1.8 Volts
If the S2 pin is at a M level during power up, a 0 state will be latched into the devices internal state register.
Block Diagram
XIN
XOUT
PLL1
CPU_STP#
IREF
VSSIREF
S(0:2)
MULT0
VTT_PG#
PCI_STP#
PLL2
PD#
WD
Logic
SDATA
SCLK
VDDA
I2C
Logic
66B[1:3]/3V66[2:5]
Power
Up Logic
66IN/3V66-5
/2
Pin Configuration
REF
VDD
XIN
XOUT
VSS
PCIF0
PCIF1
PCIF2
VDD
VSS
PCI0
PCI1
PCI2
PCIE
VDD
VSS
PCI4
PCI5
PCI6
VDD
VSS
66B0/3V66_2
66B1/3V66_3
66B2/3V66_4
66IN/3V66_5
PD#
VDDA
VSSA
VTT_PG#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF
S1
S0
CPU_STP#
CPU0
CPU/0
VDD
CPU1
CPU/1
VSS
VDD
CPU2
CPU/2
MULT0
IREF
VSSIREF
S2
48MUSB
48MDOT
VDD
VSS
3V66_1/VCH
PCI_STP#
3V66_0
VDD
VSS
SCLK
SDATA
CPU(0:2)
CPU/(0:2)
3V66_0
3V66_1/VCH
PCI_F(0:2)
PCI(0:2,4:6)
48M USB
48M DOT
PCIE
C9832
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07109 Rev. **
5/24/2001
Page 1 of 24
Approved Product
C9832H
High Performance Pentium® 4 Clock Synthesizer
Pin Description
PIN
2
3
52, 51, 49,
48, 45, 44
10, 11, 12,
16, 17, 18
5, 6, 7
NAME
XIN
XOUT
CPU, CPU/
(0:2)
PCI(0:2, 4:6)
PCIF (0:2)
PWR
VDD
VDD
VDDP
VDD
I/O
I
O
O
O
O
Description
Oscillator Buffer Input. Connect to a crystal or to an external clock.
Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at XIN.
Differential host output clock pairs. See the frequency table on page one
of this data sheet for frequencies and functionality.
PCI Clock Outputs. See Frequency Table on page one of this data sheet.
33Mhz PCI clocks, which are
÷2
copies of 66IN or 3V66 clocks, may be
free running (not stopped when PCI_STP# is asserted low) or may be
stoppable depending on the programming of I2C register Byte3, Bits
(3:5).
Early PCI clock. Leads all other PCI clocks by 1ns typ.
Buffered Output copy of the device’s XIN clock.
Current reference programming input for CPU buffers. A resistor is
connected between this pin and VSSIREF. See CPU Clock current Select
Table in page 18 of this data sheet.
Qualifying input that latches S (0:2) and MULT0. When this input is at a
logic low, the S (0:2) and MULT0 are latched
Fixed 48MHz USB Clock Outputs.
Fixed 48MHZ DOT Clock Outputs.
3.3 Volt 66 MHz fixed frequency clock.
2
3.3 volt clock selectable with I C byte0, Bit5, when Byte5, Bit5. When
Byte 0 Bit 5 is at a logic 1, then this pin is a 48M output clock. When
byte0, Bit5 is a logic 0, then this is a 66M output clock (default).
This pin is a power down mode pin. A logic low level causes the device
to enters a power down state. All internal logic is turned off except for the
2
I C logic. All output buffers are stopped. See the Power Down section of
this data sheet.
Programming input selection for CPU clock current multiplier. See CPU
Clock Current Select Function Table.
Frequency Select Inputs. See Frequency Table on page 1.
2
Serial Data Input. Conforms to the Philips I C specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open
drain output when acknowledging or transmitting data. See application
note AN-0022
2
Serial Clock Input. Conforms to the Philips I C specification. See
application note AN-0022.
Frequency Select input. See Frequency Table on page 1. This is a Tri
level input, which is driven high, low or driven to an intermediate level.
PCI Clock Disable Input. When asserted low, PCI (0:6) clocks are
synchronously disabled in a low state. This pin does not effect PCIF (0:2)
clocks’ outputs if they are programmed to be PCIF clocks via the device’s
2
I C interface.
13
56
42
PCIE
REF
IREF
VDD
VDD
VDD
O
O
I
28
39
38
33
35
VTT_PG#
48MUSB
48MDOT
3V66_0
3V66_1/VCH
VDD
VDD48
VDD48
VDD
VDD
I
O
O
O
O
25
PD#/
VDD
PU
I
43
55, 54
29
MULT0
S(0,1)
SDATA
I
I
I
I
I
30
40
34
SCLK
S2
PCI_STP#
I
VDD
VDD
I
I
T
I
PU
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07109 Rev. **
5/24/2001
Page 2 of 24
Approved Product
C9832H
High Performance Pentium® 4 Clock Synthesizer
Pin Description (Cont.)
PIN
53
NAME
CPU_STP#
PWR
VDD
I/O
I
PU
I/O
O
PWR
Description
CPU Clock Disable Input. When asserted low, CPU (0:2) clocks are
synchronously disabled in a low state and CPU/(0:2) clocks are
synchronously disabled in an open state.
Input connection for 66CLK(0:2) output clock buffers if S2 = 1, or output
clock for fixed 66 MHz clock if S2=0. See table on page 1
3.3 volt clock outputs. These clocks are buffered copies of the 66IN
clock or fixed at 66 MHz. See table on page 1
3.3V Power Supply
24
21, 22, 23
1, 8, 14,
19, 32, 37,
46, 50
4, 9, 15,
20, 27, 31,
36, 47
41
66IN/3V66_5
66B(0:2)/
3V66(2:4)
VDD
VDD
VDD
VSS
PWR
Common Ground
VSSIREF
PWR
26
VDDA
-
PWR
Current reference programming input for CPU buffers. A resistor is
connected between this pin and IREF. See CPU Clock current Select
Table in page 18 of this data sheet. This pin should also be returned to
device VSS.
Analog power input. Used for PLL and internal analog circuits. Is also
specifically used to detect and determine when power is at an
acceptable level to enable the device to operate.
PU = Internal Pull-Up. PD = Internal Pull-Down. T = Tri level logic input with valid logic voltages of LOW=<0.8V, T=1.0-1.8V and
HIGH=>2.0V
2-Wire SMBus Control Interface
The 2-wire control interface implements a read/write slave only interface according to Philips I²C specification. (See
Application Note AN-0022).
The device will accept data written to the D2 address and data may read back from address D3. It will not respond to
any other addresses, and previously set control registers are retained as long as power in maintained on the device.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional bytes must be sent:
1) “Command
Code
“ byte, and
2) “Byte
Count”
byte.
Although the data (bits) in the command is considered “don’t care”; it must be sent and will be acknowledged.
After the Command Code and the Byte Count have been acknowledged, the sequence (Byte 0, Byte 1, and Byte 2)
described below will be valid and acknowledged.
Note:
The Pin# column lists the relevant pin number where applicable. The @Pup column gives the default state at
power up.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07109 Rev. **
5/24/2001
Page 3 of 24
Approved Product
C9832H
High Performance Pentium® 4 Clock Synthesizer
Serial Control Registers (Cont.)
Byte 0: CPU Clock Register
Bit
@Pup
7
0
Pin#
-
Description
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
This is a Read and Write control bit.
Reserved
3V66_1/VCH frequency Select
0 = 66M selected, 1 = 48M selected
This is a Read and Write control bit.
CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is Read Only.
Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# is a
logical AND function of the internal SMBus register bit and the external PCI_STP# pin.
Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read Only.
Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read Only.
Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read Only.
6
5
0
0
-
35
4
3
2
1
0
Pin 53
Pin 34
Pin 40
Pin 55
Pin 54
44,45,48,49,
51,52
10,11,12,13,
16,17,18
-
-
-
Byte 1: CPU Clock Register
Bit
7
6
5
@Pup
Pin 43
0
0
Pin#
-
-
44,45
Description
MULT0 (Pin 43) Value. This bit is Read Only.
Reserved
Controls CPU2 functionality when CPU_STP# is asserted LOW
1 = Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
Controls CPU1 functionality when CPU_STP# is asserted LOW
1 = Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
Controls CPU0 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
CPU2 Output Control, 1 = enabled, 0 = disable HIGH and CPU/2 disables LOW
This is a Read and Write control bit.
CPU1 Output Control, 1 = enabled, 0 = disable HIGH and CPU/1 disables LOW
This is a Read and Write control bit.
CPU0 Output Control, 1 = enabled, 0 = disable HIGH and CPU/0 disables LOW
This is a Read and Write control bit.
Byte 3: PCI_F Clock and 48M Control Register
(all bits are read and write functional)
Bit
7
6
5
@Pup
1
1
0
Pin#
38
39
7
Description
48MDOT Output Control
1 = enabled, 0 = forced LOW
48MUSB Output Control
1 = enabled, 0 = forced LOW
PCI_STP#, control of PCI_F2.
0 = Free Running, 1 = Stopped when
PCI_STP# is LOW
PCI_STP#, control of PCI_F1.
0 = Free Running, 1 = Stopped when
PCI_STP# is LOW
PCI_STP#, control of PCI_F0.
0 = Free Running, 1 = Stopped when
PCI_STP# is LOW
PCI_F2 Output Control
1=running, 0=forced LOW
PCI_F1 Output Control
1= running, 0=forced LOW
PCI_F0 Output Control
1= running, 0=forced LOW
5/24/2001
Page 4 of 24
4
0
48,49
3
0
51,52
2
1
0
1
1
1
44,45
48,49
51,52
Byte 2: PCI Clock Control Register
(all bits are read and write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
1
1
1
1
1
1
Pin#
-
18
17
16
13
12
11
10
Description
Reserved
PCI6 Output Control
1 = enabled, 0 = forced LOW
PCI5 Output Control
1 = enabled, 0 = forced LOW
PCI4 Output Control
1 = enabled, 0 = forced LOW
PCIE Output Control
1 = enabled, 0 = forced LOW
PCI2 Output Control
1 = enabled, 0 = forced LOW
PCI1 Output Control
1 = enabled, 0 = forced LOW
PCI0 Output Control
1 = enabled, 0 = forced LOW
4
0
6
3
0
5
2
1
0
1
1
1
7
6
5
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07109 Rev. **
Approved Product
C9832H
High Performance Pentium® 4 Clock Synthesizer
Byte 4: DRCG Control Register
(all bits are read and write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
1
1
1
1
1
1
Pin#
-
-
33
35
24
23
22
21
Description
SS2 Spread Spectrum control bit
(0=down spread, 1=Center spread)
Reserved
3V66_0 Output Enabled
1 = enabled, 0 = disabled
3V66_1/VCH Output Enable
1 = enabled, 0 = disabled
3V66_5 Output Enable
1 = enabled, 0 = disabled
66B2/3V66_4 Output Enabled
1 = enabled, 0 = disabled
66B1/3V66_3 Output Enabled
1 = enabled, 0 = disabled
66B0/3V66_2 Output Enabled
1 = enabled, 0 = disabled
Byte 5: Clock control register
(all bits are read and write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
0
0
0
0
0
0
Pin#
-
-
-
-
-
-
-
-
Description
SS1 Spread Spectrum control bit
SS0 Spread Spectrum control bit
66IN to 66M delay Control MSB
66IN to 66M delay Control LSB
48MDOT edge rate control MSB
48MDOT edge rate control LSB
USB edge rate control MSB
USB edge rate control LSB
Byte 7: Watch Dog Time Stamp Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Pin#
-
-
-
-
-
-
-
-
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 6: Silicon Signature Register
(all bits are read only)
Bit
@Pup
Pin#
Description
7
0
-
Vendor Code
6
0
-
011 = IMI
5
0
-
4
0
-
3
0
-
2
0
-
1
1
-
0
1
-
Note:
When writing to this register the device will acknowledge the
write operation, but the data itself will be ignored.
Byte 8: Dial-a-Frequency™ Control Register N
(all bits are read and write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Pin#
0
0
0
0
0
0
0
0
Description
N7, MSB
N6
N5
N4
N3
N2
N3
N0, LSB
Byte 9: Dial-a-Frequency™ Control Register R
(all bits are read and write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Pin#
-
-
-
-
-
-
-
-
Description
R6 MSB
R5
R4
R3
R2
R1
R0, LSB
R and N register load gate 0=gate closed
(data is latched), 1=gate open (data is
loading from SMBus registers into R and
N)
66IN to 66M Delay Control Table
Byte5
Bit5
Bit4
0
0
0
1
1
0
1
1
Delay (ns)
4.29
4.43
3.95 (default)
3.95
Note:
See App. Notes AN0025 and AN0026 for Dial-a-Frequency
and Dial-a-db.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07109 Rev. **
5/24/2001
Page 5 of 24
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