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March 1996
NDC7002N
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description
These dual N-Channel enhancement mode power field
effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process has been designed to minimize
on-state resistance, provide rugged and reliable
performance and fast switching. These devices is
particularly suited for low voltage applications requiring a
low current high side switch.
Features
0.51A, 50V, R
DS(ON)
= 2
Ω
@ V
GS
=10V
High density cell design for low R
DS(ON)
.
Proprietary SuperSOT
TM
-6 package design using copper
lead frame for superior thermal and electrical capabilities.
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Maximum Continuous Source Current
Maximum Pulse Source Current
(Note 2)
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 0.51 A
(Note 2)
0.8
0.51
1.5
1.2
A
A
V
P
D
(
t
) =
R
θ
J A
t
)
(
T
J
−
T
A
=
R
θ
J C
R
θ
CA
t
)
+
(
T
J
−
T
A
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
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