PSD835G1-12B81I datasheet, PDF

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PSD835G1-12B81I: Description512K X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80; Categorysemiconductor The embedded processor and controller; File Size747KB，120 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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PSD835G1-12B81I Overview

512K X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80

PSD835G1-12B81I Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	80
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	3 V
Rated supply voltage	3.3 V
Number of input and output buses	52
Processing package description	PLASTIC, TQFP-80
state	DISCONTINUED
packaging shape	SQUARE
Package Size	FLATPACK, THIN PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
Microprocessor type	PIA-GENERAL PURPOSE
Number of ports	7

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PSD835G2

Flash PSD, 5 V supply, for 8-bit MCUs

4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM

Features

■

Flash in-system programmable (ISP)

peripheral for 8-bit MCUs

Dual bank flash memories

– 4 Mbits of primary Flash memory

(8 uniform sectors, 64 Kbytes)

– 256 Kbits of secondary Flash memory with

4 sectors

– Concurrent operation: READ from one

memory while erasing and writing the other

64 Kbit of SRAM

52 reconfigurable I/O ports

Enhanced JTAG serial port

PLD with macrocells

– Over 3000 gates of PLD: CPLD and DPLD

– CPLD with 16 output macrocells (OMCs)

and 24 Rev 5 macrocells (IMCs)

– DPLD - user defined internal chip select

decoding

52 individually configurable I/O port pins

They can be used for the following functions:

– MCU I/Os

– PLD I/Os

– Latched MCU address output

– Special function I/Os.

– I/O ports may be configured as open-drain

outputs.

■

Page register

– Internal page register that can be used to

expand the microcontroller address space

by a factor of 256

Programmable power management

High endurance

– 100,000 Erase/WRITE cycles of Flash

memory

– 1,000 Erase/Write cycles of PLD

– 15 year data retention

5 V±10% single supply voltage

Standby current as low as 50 µA

LQFP80 (U)

■

In-system programming (ISP) with JTAG

– Built-in JTAG compliant serial port allows

full-chip in-system programmability

– Efficient manufacturing allow easy product

testing and programming

– Use low cost FlashLINK cable with PC

Memory speed

– 70 ns Flash memory and SRAM access

time for V

= 4.5 to 5.5 V

– 90 ns Flash memory and SRAM access

time for V

= 4.5 to 5.5 V

ECOPACK

package

■

February 2009

Rev 5

1/120

www.st.com

Contents

PSD835G2

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1

In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1.1

1.1.2

1.1.3

First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Inventory build-up of preprogrammed devices . . . . . . . . . . . . . . . . . . . . 11

Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2

In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.2.1

1.2.2

1.2.3

Simultaneous READ and WRITE to Flash memory . . . . . . . . . . . . . . . . 12

Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Separate program and data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.3

PSDsoft™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

JTAG port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

In-application reprogramming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.9

Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PSD register description and address offset . . . . . . . . . . . . . . . . . . . . 24

Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.1

6.2

6.3

6.4

Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Primary Flash memory and secondary Flash memory description . . . . . 33

Memory Block Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Upper and lower block in main Flash sector . . . . . . . . . . . . . . . . . . . . . . . 33

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PSD835G2

Contents

6.5

6.6

Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

7.10

Power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Read Primary Flash Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Read the Erase/Program Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Data Polling flag (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Toggle flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Error flag (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Erase Time-out flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.1

8.2

8.3

Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.1

9.2

9.3

9.4

Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.1

10.2

10.3

Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Reset (RESET) signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

12.1

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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Contents

PSD835G2

12.2

12.3

Memory Select configuration for MCUs with separate program and data

spaces 48

Configuration modes for MCUs with separate program and data spaces 49

12.3.1

12.3.2

Separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Combined space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Memory ID registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

15.1

15.2

15.3

15.4

15.5

15.6

15.7

15.8

15.9

PSD Turbo bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Product term allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Loading and Reading the output macrocells (OMC) . . . . . . . . . . . . . . . . 60

The OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

15.10 External chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

16.1

16.2

PSD interface to a multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . . . . . 67

PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 67

MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

16.3

16.4

16.5

16.6

16.7

80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

17.1

17.2

17.3

General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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PSD835G2

Contents

17.4

17.5

17.6

17.7

17.8

17.9

PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Data port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

17.10 Port configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

17.11 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

17.12 Direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

17.13 Drive Select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

17.14 Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

17.15 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

17.16 Data Out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

17.17 Output macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

17.18 OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

17.19 Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

17.20 Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

17.21 Ports A,B and C – functionality and structure . . . . . . . . . . . . . . . . . . . . . 83

17.22 Port D – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

17.23 Port E – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

17.24 Port F – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

17.25 Port G – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Automatic Power-down (APD) unit and Power-down mode . . . . . . . . . . . 89

18.1.1

Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

18.1

18.2

18.3

18.4

18.5

18.6

Other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

PLD Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Reset timing and device status at Reset . . . . . . . . . . . . . . . . . . . . . . . . 93

19.1

Power-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5/120

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