LM124, LM224, LM324
Low power quad operational amplifiers
Features
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Wide gain bandwidth: 1.3 MHz
Input common-mode voltage range includes
ground
Large voltage gain: 100 dB
Very low supply current per amplifier: 375 µA
Low input bias current: 20 nA
Low input offset voltage: 5 mV max.
Low input offset current: 2 nA
Wide power supply range:
– Single supply: +3 V to +30 V
Dual supplies: ±1.5 V to ±15 V
D
SO-14
(Plastic micropackage)
N
DIP14
(Plastic package)
Description
The LM124, LM224 and LM324 consist of four
independent, high gain, internally frequency-
compensated operational amplifiers. They
operate from a single power supply over a wide
range of voltages. Operation from split power
supplies is also possible and the low power
supply current drain is independent of the
magnitude of the power supply voltage.
P
TSSOP-14
(Thin shrink small outline package)
Q
QFN16 3x3
(Plastic micropackage)
June 2011
Doc ID 2156 Rev 7
1/19
www.st.com
19
Pin and schematic diagram
LM124, LM224, LM324
1
Pin and schematic diagram
Figure 1.
Pin connections (top view)
Output 1 1
Inverting Input 1 2
Non-inverting Input 1 3
V
CC
+ 4
Non-inverting Input 2
Inverting Input 2
5
6
+
-
+
-
-
+
-
+
14 Output 4
13 Inverting Input 4
12 Non-inverting Input 4
11 V
CC
-
10 Non-inverting Input 3
9
8
Inverting Input 3
Output 3
Output 2 7
OUT1
OUT1
OUT4
OUT4
IN1-
IN1-
16
IN4-
IN4-
15
14
14
13
13
IN1+
VCC+
NC
IN2+
IN2
1
12
IN4+
VCC-
NC
IN3+
IN3
2
11
3
10
4
9
5
6
7
IN2-
OUT2
Figure 2.
Schematic diagram (1/4 LM124)
2/19
Doc ID 2156 Rev 7
OUT3
IN3-
8
LM124, LM224, LM324
Absolute maximum ratings
2
Table 1.
Symbol
V
CC
V
in
V
id
Absolute maximum ratings
Absolute maximum ratings
Parameter
Supply voltage
Input voltage
(1)
Differential input voltage
(2)
Output short-circuit duration
(3)
I
in
T
oper
T
stg
T
j
LM124
LM224
±16 or 32
-0.3 to 32
32
Infinite
mA
°C
°C
°C
LM324
Unit
V
V
V
5 mA in DC or 50 mA in AC (duty cycle = 10%, T=1s)
Input current
(4)
: V
in
driven negative
(5)
Input current : V
in
driven positive above
AMR value
0.4
Operating free-air temperature range
Storage temperature range
Maximum junction temperature
Thermal resistance junction to ambient
(6)
SO14
TSSOP14
DIP14
QFN16 3x3
Thermal resistance junction to case
SO14
TSSOP14
DIP14
QFN16
HBM: human body model
(7)
-55 to +125
-40 to +105
-65 to +150
150
103
100
83
45
31
32
33
14
250
150
1500
0 to +70
R
thja
°C/W
R
thjc
°C/W
ESD
MM: machine model
(8)
CDM: charged device model
(9)
V
1. Either or both input voltages must not exceed the magnitude of V
CC+
or V
CC-
. All voltage values, except differential voltages
are with respect to ground terminal.
2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal.
3. Short-circuits from the output to V
CC
can cause excessive heating if V
CC
> 15 V. The maximum output current is
approximately 40 mA independent of the magnitude of V
CC
. Destructive dissipation can result from simultaneous short-
circuits on all amplifiers.
4. This input current only exists when the voltage at any of the input leads is driven negative. It is due to the collector-base
junction of the input PNP transistor becoming forward-biased and thereby acting as input diode clamp. In addition to this
diode action, there is NPN parasitic action on the IC chip. This transistor action can cause the output voltages of the op-
amps to go to the V
CC
voltage level (or to ground for a large overdrive) for the time during which an input is driven negative.
This is not destructive and normal output is restored for input voltages above -0.3 V.
5. The junction base/substrate of the input PNP transistor polarized in reverse must be protected by a resistor in series with
the inputs to limit the input current to 400 µA max (R = (Vin - 32 V)/400 µA).
6. Short-circuits can cause excessive heating. Destructive dissipation can result from simultaneous short-circuits on all
amplifiers. These are typical values given for a single layer board (except for TSSOP, a two-layer board).
7. Human body model, 100 pF discharged through a 1.5 kΩ resistor into pin of device.
8. Machine model ESD: a 200 pF capacitor is charged to the specified voltage, then discharged directly into the IC with no
external series resistor (internal resistor < 5
Ω),
into pin-to-pin of device.
9. Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to
ground.
Doc ID 2156 Rev 7
3/19
Electrical characteristics
LM124, LM224, LM324
3
Electrical characteristics
Table 2.
Symbol
Input offset voltage
(1)
T
amb
= +25° C
LM124-LM224
LM324
T
min
≤
T
amb
≤
T
max
LM124-LM224
LM324
I
io
Input offset current
T
amb
= +25° C
T
min
≤
T
amb
≤
T
max
Input bias current
(2)
T
amb
= +25° C
T
min
≤
T
amb
≤
T
max
Large signal voltage gain
V
CC+
= +15 V, R
L
= 2 kΩ, V
o
= 1.4 V to 11.4 V
T
amb
= +25° C
T
min
≤
T
amb
≤
T
max
Supply voltage rejection ratio (R
s
≤
10 kΩ)
V
CC+
= 5 V to 30 V
T
amb
= +25° C
T
min
≤
T
amb
≤
T
max
Supply current, all Amp, no load
T
amb
= +25° C
V
CC
= +5 V
V
CC
= +30 V
T
min
≤
T
amb
≤
T
max
V
CC
= +5 V
V
CC
= +30 V
Input common mode voltage range
V
CC
= +30 V
(3)
T
amb
= +25° C
T
min
≤
T
amb
≤
T
max
Common mode rejection ratio (R
s
≤
10 kΩ)
T
amb
= +25° C
T
min
≤
T
amb
≤
T
max
Output current source (V
id
= +1 V)
V
CC
= +15 V, V
o
= +2 V
2
V
CC+
= +5 V, V
CC-
= ground, V
o
= 1.4 V, T
amb
= +25° C (unless otherwise
specified)
Parameter
Min.
Typ.
Max.
Unit
2
V
io
5
7
7
9
30
100
150
300
mV
nA
I
ib
20
nA
A
vd
50
25
100
V/mV
SVR
65
65
110
dB
I
CC
0.7
1.5
0.8
1.5
1.2
3
1.2
3
mA
V
icm
0
0
70
60
20
80
V
CC
-1.5
V
CC
-2
V
CMR
dB
I
source
40
70
mA
4/19
Doc ID 2156 Rev 7
LM124, LM224, LM324
Table 2.
Symbol
Electrical characteristics
V
CC+
= +5 V, V
CC-
= ground, V
o
= 1.4 V, T
amb
= +25° C (unless otherwise
specified) (continued)
Parameter
Min.
Typ.
Max.
Unit
I
sink
Output sink current (V
id
= -1 V)
V
CC
= +15 V, V
o
= +2 V
V
CC
= +15 V, V
o
= +0.2 V
High level output voltage
V
CC
= +30 V
T
amb
= +25° C, R
L
= 2 kΩ
T
min
≤
T
amb
≤
T
max
T
amb
= +25° C, R
L
= 10 kΩ
T
min
≤
T
amb
≤
T
max
V
CC
= +5 V, R
L
= 2 kΩ
T
amb
= +25°C
T
min
≤
T
amb
≤
T
max
10
12
20
50
mA
µA
V
OH
26
26
27
27
3.5
3
27
28
V
V
OL
Low level output voltage (R
L
= 10 kΩ)
T
amb
= +25°C
T
min
≤
T
amb
≤
T
max
Slew rate
,
V
CC
= 15 V, V
i
= 0.5 to 3 V, R
L
= 2 kΩ C
L
= 100 pF,
unity gain
Gain bandwidth product
,
V
CC
= 30 V, f = 100 kHz, V
in
= 10 mV, R
L
= 2 kΩ
C
L
= 100 pF
Total harmonic distortion
f = 1 kHz, A
v
= 20 dB, R
L
= 2 kΩ, V
o
= 2 V
pp
,
C
L
= 100 pF, V
CC
= 30 V
Equivalent input noise voltage
f = 1 kHz, R
s
= 100
Ω,
V
CC
= 30 V
Input offset voltage drift
Input offset current drift
Channel separation
(4)
1 kHz
≤
f
≤
20 kHZ
5
20
20
mV
SR
0.4
V/µs
GBP
1.3
MHz
THD
0.015
%
e
n
DV
io
DI
io
V
o1
/V
o2
40
7
10
120
30
200
nV
-----------
-
Hz
µV/°C
pA/°C
dB
1. V
o
= 1.4 V, R
s
= 0
Ω,
5 V < V
CC+
< 30 V, 0 < V
ic
< V
CC+
- 1.5 V.
2. The direction of the input current is out of the IC. This current is essentially constant, independent of the
state of the output so there is no change in the load on the input lines.
3. The input common-mode voltage of either input signal voltage should not be allowed to go negative by
more than 0. V. The upper end of the common-mode voltage range is V
CC+
- 1.5 V, but either or both inputs
can go to +32 V without damage.
4. Due to the proximity of the external components, ensure that stray capacitance between these external
parts does not cause coupling. Coupling can be detected because this type of capacitance increases at
higher frequencies.
Doc ID 2156 Rev 7
5/19
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