NCP372
Positive and Negative
Overvoltage Protection
Controller with Internal
Low R
on
NMOS FETs and
Status FLAG
The NCP372 is able to disconnect systems from its output pin
when wrong operating conditions are detected at it’s input. The
system is both positive and negative overvoltage protected up to
±28
V.
This device uses internal NMOS, and therefore, no external device
is necessary, reducing the system cost and the PCB area of the
application board.
The NCP372 is able to instantaneously disconnect the output from
the input, due to integrated Low R
on
Power NMOS, if the input
voltage exceeds the overvoltage threshold (OVLO) or undervoltage
threshold (UVLO).
At powerup (EN pin = low level), the V
out
turns on 30 ms after the
V
in
exceeds the undervoltage threshold.
The NCP372 provides a negative going flag (FLAG) output, which
alerts the system that a fault has occurred.
In addition, the device has ESD−protected input (15 kV Air) when
bypassed with a 1.0
mF
or larger capacitor.
Features
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MARKING
DIAGRAM
1
12 PIN LLGA
MU SUFFIX
CASE 513AK
NCAI
372
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
IN
IN
GND
RES
RES
RES
1
2
3
4
5
6
12
OUT
11
10
9
8
7
•
•
•
•
•
•
•
•
•
•
Overvoltage Protection up to 28 V
Negative Voltage Protection down to
−28
V
Reverse Current Blocking
On−Chip Low R
DS(on)
NMOS Transistor: Typical 130 mW
Overvoltage Lockout (OVLO)
Undervoltage Lockout (UVLO)
Soft−Start
Alert
FLAG
Output
Shutdown
EN
Input
Compliance to IEC61000−4−2 (Level 4)
8.0 kV (Contact)
15 kV (Air)
•
ESD Ratings: Machine Model = B
Human Body Model = 2
•
12 Lead LLGA 3x3 mm Package
•
This is a Pb−Free and Halogen−Free Device
Applications
OUT
FLAG
EN
NC
GND
NCP372
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
•
•
•
•
•
•
Cell Phones
Camera Phones
Digital Still Cameras
Personal Digital Assistant
MP3 Players
GPS
1
Publication Order Number:
NCP372/D
©
Semiconductor Components Industries, LLC, 2010
October, 2010
−
Rev. 1
NCP372
TYPICAL APPLICATION CIRCUIT AND FUNCTIONAL BLOCK DIAGRAM
10k
Charger
Wall Adapter
U1
1
2
3
4
5
6
12
IN
OUT 11
IN
OUT 10
GND FLAG 9
RES
EN 8
NC 7
RES
RES
GND
NCP372
0
FLAG
EN
FLAG
4.7mF
EN
System
LI+BATTERY
1mF
GND
Figure 1. Typical Application Circuit
INPUT
Gate Driver
OUTPUT
VREF
Charge
Pump
EN
Block
UVLO
OVLO
Control
Logic
and
Timer
FLAG
Thermal
Shutdown
EN
Figure 2. Functional Block Diagram
GND
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2
NCP372
PIN FUNCTION DESCRIPTION
Pin
1, 2
Name
IN
Type
POWER
Description
Input voltage pins. These pins are connected to the power supply. A 1
mF
low ESR ceramic capacitor, or
larger, must be connected between these pins and GND. The two IN pins must be hardwired to common
supply.
Main Ground
Reserved pin. This pin must be connected to GND.
Reserved pin. This pin must be connected to GND.
Reserved pin. This pin must be connected to GND.
This pin must be directly hardwired to GND or through a pull down resistor with a 1 MW maximum value.
Not Connected
Enable Pin. The device enters into shutdown mode when this pin is tied to a high level. In this case the
output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to GND
to a pull−down or to an I/O pin. This pin does not have an impact on the fault detection.
Fault Indication Pin. This pin allows an external system to detect fault condition. The pin goes low when
input voltage exceeds OVLO threshold, drops below UVLO threshold, or internal temperature exceeds
thermal shutdown limit. Since the pin is open drain functionality, an external pull up resistor to VBat must
be added (10 kW minimum value).
Output Voltage Pin. This pin follows IN pins when “no input fault” is detected. The output is disconnected
from the V
IN
power supply when the input voltage is under the UVLO threshold or above OVLO threshold
or thermal shutdown limit is exceeded.
The PAD1 is used to dissipate the internal MOSFET thermal energy and must be soldered to an isolated
PCB area. The area must not be connected to any potential other than a completely isolated one. See
PCB Recommendations on page 10.
3
4
5
6
7
8
9
GND
RES
RES
RES
GND
NC
EN
POWER
INPUT
INPUT
INPUT
POWER
NC
INPUT
10
FLAG
OUTPUT
11,12
OUT
OUTPUT
13
PAD1
POWER
MAXIMUM RATINGS
Rating
Minimum Voltage (IN to GND)
Minimum Voltage (All others to GND)
Maximum Voltage (IN to GND)
Maximum Voltage (OUT to GND)
Maximum Voltage (All others to GND)
Maximum DC Current
Thermal Resistance, Junction−to−Air, (Note 1)
Operating Ambient Temperature Range
Storage Temperature Range
Junction Operating Temperature
ESD Withstand Voltage (IEC 61000−4−2)
Human Body Model (HBM), Model = 2, (Note 2)
Machine Model (MM) Model = B, (Note 3)
Moisture Sensitivity
Symbol
Vmin
in
Vmin
Vmax
in
Vmax
out
Vmax
Imax
R
qJA
T
A
T
STG
T
J
Vesd
Value
−30
−0.3
30
10
7
2.5
200
−40
to +85
−65
to +150
150
15kV air, 8kV contact
2000V
200V
Level 1
Unit
V
V
V
V
V
A
°C/W
°C
°C
°C
kV
V
V
MSL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The R
qJA
is highly dependent on the PCB heat sink area (connected to PAD1). See PCB recommendation paragraph.
2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
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3
NCP372
ELECTRICAL CHARACTERISTICS
(V
in
= 5 V, Minimum/Maximum limits at
−40°C
< T
A
< +85°C unless otherwise noted. Typical
values are at T
A
= +25°C)
Characteristics
Input Voltage Range
Input Voltage
Undervoltage Lockout Threshold
Undervoltage Lockout
Hysteresis
Over voltage Lockout Threshold
NCP372MUAITXG
Overvoltage Lockout Hysteresis
V
in
to V
out
Resistance
Symbols
V
in
Vin
min
UVLO
UVLO
hyst
OVLO
OVLO
hyst
R
DS(on)
Conditions
EN = low or high, V
out
= 0 V
EN = low or high, V
out
= 4.25V
Vin falls below UVLO Threshold
V
in
rises above UVLO Threshold + UVLO
hyst
V
in
rises above OVLO threshold
V
in
falls below to OVLO
−
OVLO
hyst
V
in
= 5 V, EN = low, Load Connected to V
out
V
in
= 5 V, EN = low,
Load Connected to V
out
@ 25°C
No Load. EN = high, V
in
connected
25°C
Overtemperature Range
1.2 V < V
in
< UVLO
Sink 50
mA
on FLAG Pin
V
in
> OVLO, Sink 1 mA on FLAG Pin
FLAG Leakage Current
EN Voltage High
EN Voltage Low
EN Leakage Current
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
TIMINGS
Start Up Delay
FLAG Going Up Delay
Turn Off Delay
Alert Delay
Disable Time
NOTE:
t
on
t
start
t
off
t
stop
t
dis
From V
in
> UVLO to V
out
w
0.3 V
From V
out
> 0.3 V to FLAG = 1.2 V
From V
in
> OVLO to V
out
v
0.3 V
V
in
Increasing from 5 V to 8 V at 3 V/ms
From V
in
> OVLO to FLAG
v
0.4 V See Figure 3
and 9 V
in
Increasing from 5 V to 8 V at 3 V/ms
EN = 0.4 V to 1.2 V to V
out
v
0.3 V
20
20
30
30
1.5
1.5
2.5
40
40
5.0
ms
ms
ms
ms
ms
FLAG
leak
V
ihEN
V
ilEN
EN
leak
T
SD
T
SDHYST
V
in
connected
V
in
disconnected
200
1.0
150
30
FLAG Level = 5.5 V
1.2
0.55
1.0
Min
−28
−24
2.6
45
6.0
60
2.7
60
6.3
80
130
130
90
200
30
2.8
75
6.6
100
220
200
170
260
310
400
400
nA
V
V
nA
°C
°C
mA
mA
mV
Typ
Max
28
Unit
V
V
V
mV
V
mV
mW
Input Standby Current
Input Supply Quiescent Current
FLAG Output Low Voltage
Idd
STD
Idd
IN
Vol
flag
Electrical parameters are guaranteed by correlation across the full range of temperature.
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4
NCP372
TIMING DIAGRAMS
<OVLO
V
in
V
in
−
(R
DS(on)
t
start
FLAG
FLAG
1.2 V
t
stop
0.4 V
I)
V
out
V
in
−
(R
DS(on)
I)
OVLO
t
off
0.3 V
V
in
UVLO
t
on
V
out
0.3 V
Figure 3. Startup
Figure 4. Shutdown on Overvoltage Detection
EN
EN
V
out
V
in
−
(R
DS(on)
FLAG
1.2 V
t
dis
I)
0.3 V
FLAG
V
in
1.2 V
OVLO
UVLO
t
on
+ t
start
Figure 5. Disable on EN = 1
Figure 6. FLAG Response with EN = 1
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