LPC82x
32-bit ARM Cortex-M0+ microcontroller; up to 32 kB flash and
8 kB SRAM; 12-bit ADC; comparator
Rev. 1.2 — 11 October 2016
Product data sheet
1. General description
The LPC82x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The LPC82x support up to 32 KB of flash memory and
8 KB of SRAM.
The peripheral complement of the LPC82x includes a CRC engine, four I
2
C-bus
interfaces, up to three USARTs, up to two SPI interfaces, one multi-rate timer,
self-wake-up timer, and state-configurable timer with PWM function (SCTimer/PWM), a
DMA, one 12-bit ADC and one analog comparator, function-configurable I/O ports through
a switch matrix, an input pattern match engine, and up to 29 general-purpose I/O pins.
For additional documentation related to the LPC82x parts, see
Section 18.
2. Features and benefits
System:
ARM Cortex-M0+ processor (revision r0p1), running at frequencies of up to
30 MHz with single-cycle multiplier and fast single-cycle I/O port.
ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
System tick timer.
AHB multilayer matrix.
Serial Wire Debug (SWD) with four break points and two watch points. JTAG
boundary scan (BSDL) supported.
MTB
Memory:
Up to 32 KB on-chip flash programming memory with 64 Byte page write and
erase. Code Read Protection (CRP) supported.
8 KB SRAM.
ROM API support:
Boot loader.
On-chip ROM APIs for ADC, SPI, I2C, USART, power configuration (power
profiles) and integer divide.
Flash In-Application Programming (IAP) and In-System Programming (ISP).
Digital peripherals:
High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 29
General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,
programmable open-drain mode, input inverter, and digital filter. GPIO direction
control supports independent set/clear/toggle of individual bits.
High-current source output driver (20 mA) on four pins.
NXP Semiconductors
LPC82x
32-bit ARM Cortex-M0+ microcontroller
High-current sink driver (20 mA) on two true open-drain pins.
GPIO interrupt generation capability with boolean pattern-matching feature on eight
GPIO inputs.
Switch matrix for flexible configuration of each I/O pin function.
CRC engine.
DMA with 18 channels and 9 trigger inputs.
Timers:
State Configurable Timer (SCTimer/PWM) with input and output functions
(including capture and match) for timing and PWM applications. Each
SCTimer/PWM input is multiplexed to allow selecting from several input sources
such as pins, ADC interrupt, or comparator output.
Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to
four programmable, fixed rates.
Self-Wake-up Timer (WKT) clocked from either the IRC, a low-power,
low-frequency internal oscillator, or an external clock input in the always-on power
domain.
Windowed Watchdog timer (WWDT).
Analog peripherals:
One 12-bit ADC with up to 12 input channels with multiple internal and external
trigger inputs and with sample rates of up to 1.2 Msamples/s. The ADC supports
two independent conversion sequences.
Comparator with four input pins and external or internal reference voltage.
Serial peripherals:
Three USART interfaces with pin functions assigned through the switch matrix and
one common fractional baud rate generator.
Two SPI controllers with pin functions assigned through the switch matrix.
Four I
2
C-bus interfaces. One I2C supports Fast-mode Plus with 1 Mbit/s data rates
on two true open-drain pins and listen mode. Three I2Cs support data rates up to
400 kbit/s on standard digital pins.
Clock generation:
12 MHz internal RC oscillator trimmed to 1.5 % accuracy that can optionally be
used as a system clock.
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the system oscillator, the external clock
input, or the internal RC oscillator.
Clock output function with divider that can reflect all internal clock sources.
Power control:
Power consumption in active mode as low as 90 uA/MHz in low-current mode
using the IRC as the clock source.
Integrated PMU (Power Management Unit) to minimize power consumption.
Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode.
Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI, and
I2C peripherals.
Timer-controlled self wake-up from Deep power-down mode.
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
LPC82x
Product data sheet
Rev. 1.2 — 11 October 2016
2 of 82
NXP Semiconductors
LPC82x
32-bit ARM Cortex-M0+ microcontroller
Power-On Reset (POR).
Brownout detect (BOD).
Unique device serial number for identification.
Single power supply (1.8 V to 3.6 V).
Operating temperature range -40 °C to +105 °C.
Available in a TSSOP20 and HVQFN33 (5x5) package.
3. Applications
Sensor gateways
Industrial
Gaming controllers
8/16-bit applications
Consumer
Climate control
Simple motor control
Portables and wearables
Lighting
Motor control
Fire and security applications
4. Ordering information
Table 1.
Ordering information
Package
Name
LPC824M201JHI33
LPC822M101JHI33
LPC824M201JDH20
LPC822M101JDH20
HVQFN33
HVQFN33
TSSOP20
TSSOP20
Description
Version
HVQFN: plastic thermal enhanced very thin quad flat package; no leads; n/a
33 terminals; body 5
5
0.85 mm
HVQFN: plastic thermal enhanced very thin quad flat package; no leads; n/a
33 terminals; body 5
5
0.85 mm
plastic thin shrink small outline package; 20 leads; body width 4.4 mm
plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
SOT360-1
Type number
4.1 Ordering options
Table 2.
Ordering options
Flash/ SRAM/
KB
KB
32
16
32
16
8
4
8
4
USART
3
3
3
3
I
2
C
4
4
4
4
SPI
2
2
2
2
ADC
channels
12
12
5
5
Comparator
Y
Y
Y
y
GPIO
29
29
16
16
Package
HVQFN33
HVQFN33
TSSOP20
TSSOP20
Type number
LPC824M201JHI33
LPC822M101JHI33
LPC824M201JDH20
LPC822M101JDH20
LPC82x
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1.2 — 11 October 2016
3 of 82
NXP Semiconductors
LPC82x
32-bit ARM Cortex-M0+ microcontroller
5. Marking
20
Terminal 1 index area
Terminal 1 index area
1
aaa-014766
aaa-014382
Fig 1.
TSSOP20 package marking
Fig 2.
HVQFN33 package marking
The HVQFN33 packages typically have the following top-side marking:
82xJ
xx xx
yywwxR
The TSSOP20 packages typically have the following top-side marking:
LPC82x
Mx01J
xxxxxxxx
zzywwxR
In the last line, field ‘y’ or ‘yy’ states the year the device was manufactured. Field ‘ww’
states the week the device was manufactured during that year. Field ‘R’ states the chip
revision.
LPC82x
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1.2 — 11 October 2016
4 of 82
NXP Semiconductors
LPC82x
32-bit ARM Cortex-M0+ microcontroller
6. Block diagram
LPC82xM
SWCLK, SWD
29 x
PIO0
HIGH-SPEED
GPIO
TEST/DEBUG
INTERFACE
PIN INTERRUPTS/
PATTERN MATCH
INPUT MUX
ARM
CORTEX-M0+
FLASH
16/32 KB
SRAM
4/8 KB
slave
slave
ROM
slave
SCT_PIN[3:0]
SCTIMER/
PWM
slave
SCT_OUT[6:0]
AHB TO APB
BRIDGE
AHB-LITE BUS
slave
CRC
master
DMA
TXD, RTS
RXD, CTS
SCLK
29 x
SWITCH
MATRIX
SCK, SSEL
MISO, MOSI
SPI0/1
SCL
SDA
XTALOUT
XTALIN
XTAL
SYSCON
I
2
C0/1/2/3
USART0/1/2
WWDT
IOCON
MULTI-RATE TIMER
PMU
SELF
WAKE-UP TIMER
ALWAYS-ON POWER DOMAIN
RESET, CLKIN
CLKOUT
IRC
ADC_[11:0]
ADC
WDOsc
BOD
ACMP_I[4:1]
VDDCMP
ACMP_O
POR
COMPARATOR
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
clocks and
controls
aaa-014399
Gray-shaded blocks show peripherals that can provide hardware triggers or fixed DMA requests for DMA transfers.
Fig 3.
LPC82x block diagram
LPC82x
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1.2 — 11 October 2016
5 of 82
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