74LVC373APW-Q100J datasheet, PDF

Datasheet> All Categories > logic> logic> 74LVC373APW-Q100J

74LVC373APW-Q100J: DescriptionVoltage-Power: 1.65V ~ 3.6V Logic type: D-type transparent latch Output type: Tri-state Series: 74LVC; Categorylogic logic; File Size720KB，19 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com; Environmental Compliance

Download Datasheet Parametric Compare View All

74LVC373APW-Q100J Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	74LVC373APW-Q100J	-	-	View	Buy Now

74LVC373APW-Q100J Overview

Voltage-Power: 1.65V ~ 3.6V Logic type: D-type transparent latch Output type: Tri-state Series: 74LVC

74LVC373APW-Q100J Parametric

Parameter Name	Attribute value
Brand Name	Nexperia
Is it Rohs certified?	conform to
Maker	Nexperia
Parts packaging code	TSSOP2
package instruction	4.40 MM, PLASTIC, MO-153, SOT360-1, TSSOP-20
Contacts	20
Manufacturer packaging code	SOT360-1
Reach Compliance Code	compliant
Samacsys Description	74LVC373A-Q100 - Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state@en-us
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G20
length	6.5 mm
Logic integrated circuit type	BUS DRIVER
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)	19.3 ns
Filter level	AEC-Q100
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	4.4 mm
Base Number Matches	1

Preview

Download Datasheet

View All

74LVC373A-Q100

Octal D-type transparent latch with 5 V tolerant

inputs/outputs; 3-state

Rev. 1 — 17 April 2013

Product data sheet

1. General description

The 74LVC373A-Q100 consists of eight D-type transparent latches, featuring separate

D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch

enable input (pin LE) and an output enable input (pin OE) are common to all internal

latches.

When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this

condition, the latches are transparent, that is, a latch output changes each time its

corresponding D-input changes. When pin LE is LOW, the latches store the information

that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of

pin LE. When pin OE is LOW, the contents of the eight latches are available at the

Q-outputs (pins Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance

OFF-state. Operation of input pin OE does not affect the state of the latches. Inputs can

be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to

the outputs. These features allow the use of these devices as translators in mixed 3.3 V

and 5 V applications. The 74LVC373A-Q100 is functionally identical to the

74LVC573A-Q100, but has a different pin arrangement.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits



Automotive product qualification in accordance with AEC-Q100 (Grade 1)



Specified from

40 C

to +85

C

and from

40 C

to +125

C



5 V tolerant inputs/outputs for interfacing with 5 V logic



Wide supply voltage range from 1.2 V to 3.6 V



CMOS low power consumption



Direct interface with TTL levels



High-impedance outputs when V

= 0 V



Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)



JESD8-C/JESD36 (2.7 V to 3.6 V)



ESD protection:



MIL-STD-883, method 3015 exceeds 2000 V



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0

)

74LVC373APW-Q100J Related Products

	74LVC373APW-Q100J	74LVC373AD-Q100J	74LVC373ADB-Q100J	74LVC373ABQ-Q100X
Description	Voltage-Power: 1.65V ~ 3.6V Logic type: D-type transparent latch Output type: Tri-state Series: 74LVC	IC TRANSP LATCH OCTAL D 20SOIC	IC TRANSP LATCH OCTAL D 20SSOP	IC TRANSP LATCH OCTAL D 20DHVQFN
Brand Name	Nexperia	Nexperia	Nexperia	Nexperia
Is it Rohs certified?	conform to	conform to	conform to	conform to
Maker	Nexperia	Nexperia	Nexperia	Nexperia
Parts packaging code	TSSOP2	SOP	SSOP2	QFN
package instruction	4.40 MM, PLASTIC, MO-153, SOT360-1, TSSOP-20	7.50 MM, PLASTIC, MS-013, SOT163-1, SOP-20	5.30 MM, PLASTIC, MO-150, SOT339-1, SSOP-20	2.50 X 4.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT764-1, DHVQFN-20
Contacts	20	20	20	20
Manufacturer packaging code	SOT360-1	SOT163-1	SOT339-1	SOT764-1
Reach Compliance Code	compliant	compliant	compliant	compliant
Samacsys Description	74LVC373A-Q100 - Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state@en-us	74LVC373A-Q100 - Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state@en-us	74LVC373A-Q100 - Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state@en-us	74LVC373A-Q100 - Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state@en-us
series	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PQCC-N20
length	6.5 mm	12.8 mm	7.2 mm	4.5 mm
Logic integrated circuit type	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER
Number of digits	8	8	8	8
Number of functions	1	1	1	1
Number of ports	2	2	2	2
Number of terminals	20	20	20	20
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Output polarity	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	SOP	SSOP	HVQCCN
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
propagation delay (tpd)	19.3 ns	19.3 ns	19.3 ns	19.3 ns
Filter level	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100
Maximum seat height	1.1 mm	2.65 mm	2 mm	1 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	1.2 V	1.2 V	1.2 V	1.2 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal form	GULL WING	GULL WING	GULL WING	NO LEAD
Terminal pitch	0.65 mm	1.27 mm	0.65 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL	QUAD
width	4.4 mm	7.5 mm	5.3 mm	2.5 mm
Base Number Matches	1	1	1	1

Recommended Resources

Importance of Voltage Supervisors and Output Topology Selection

Ultrasonic receiver using high amplification factor integrated circuit and VMOS circuit

Using photoelectric isolation coupling to control AC load circuit

Fluorescent lamp energy-saving electronic ballast circuit 2

Soft switching circuit schematic diagram

Circuit Diagram: Samsung CE959 Microwave Oven_Page_2

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components