TC7650
Chopper Stabilized Operational Amplifier
Features
•
•
•
•
•
•
•
•
•
•
Low Input Offset Voltage: 0.7µV Typ
Low Input Offset Voltage Drift: 0.05V/°C Max
Low Input Bias Current: 10pA Max
High Impedance Differential CMOS Inputs: 10
12
High Open Loop Voltage Gain: 120dB Min.
Low Input Noise Voltage: 2.0Vp-p
High Slew Rate: 2.5V/sec.
Low Power Operation: 20mW
Output Clamp Speeds Recovery Time
Compensated Internally for Stable Unity Gain
Operation
• Direct Replacement for ICL7650
• Available in 8-Pin Plastic DIP and 14-Pin Plastic
DIP Packages
Package Type
8-Pin DIP
C
A
1
–
INPUT 2
+
INPUT 3
8
C
B
7
V
DD
TC7650CPA
6
OUTPUT
5
OUTPUT CLAMP
V
SS
4
14-Pin DIP
C
B
C
A
NC
– INPUT
+ INPUT
NC
V
SS
1
2
3
4
5
6
7
14 INT/EXT
13 EXT CLK IN
12 INT CLK OUT
Applications
•
•
•
•
•
Instrumentation
Medical Instrumentation
Embedded Control
Temperature Sensor Amplifier
Strain Gage Amplifier
TC7650CPD
11 V
DD
10 OUTPUT
9 OUTPUT CLAMP
8 C
RETN
Device Selection Table
Part
Number
TC7650CPA
NC = NO INTERNAL CONNECTION
Package
8-Pin PDIP
Temperature
Range
0°C to +70°C
0°C to +70°C
Max V
OS
5V
5V
TC7650CPD 14-Pin PDIP
2001-2012 Microchip Technology Inc.
DS21463C-page 1
TC7650
General Description
The TC7650 CMOS chopper stabilized operational
amplifier practically removes offset voltage error terms
from system error calculations. The 5V maximum V
OS
specification, for example, represents a 15 times
improvement over the industry standard OP07E. The
50nV/°C offset drift specification is over 25 times lower
than the OP07E. The increased performance elimi-
nates V
OS
trim procedures, periodic potentiometer
adjustment and the reliability problems caused by dam-
aged trimmers.
The TC7650 performance advantages are achieved
without the additional manufacturing complexity and
cost incurred with laser or "zener zap" V
OS
trim tech-
niques.
The TC7650 nulling scheme corrects both DC V
OS
errors and V
OS
drift errors with temperature. A nulling
amplifier alternately corrects its own V
OS
errors and the
main amplifier V
OS
error. Offset nulling voltages are
stored on two user supplied external capacitors. The
capacitors connect to the internal amplifier V
OS
null
points. The main amplifier input signal is never
switched. Switching spikes are not present at the
TC7650 output.
The 14-pin dual-in-line package (DIP) has an external
oscillator input to drive the nulling circuitry for optimum
noise performance. Both the 8 and 14-pin DIPs have
an output voltage clamp circuit to minimize overload
recovery time.
Functional Block Diagram
Output
Clamp
Output Clamp
Circuit
Main
Amplifier
Inputs
NULL
A
B
Output
C
B
Oscillator
14-Pin DIP Only
INT/EXT
EXT CLK IN
CLK OUT
Intermod
Compensation
B
B
Null
Amplifier
A
Null
* For 8-Pin DIP, connect to Vss
B
A
C
A
TC7650
*C
RETN
DS21463C-page 2
2001-2012 Microchip Technology Inc.
TC7650
1.0
ELECTRICAL
CHARACTERISTICS
*Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the
device at these or any other conditions above those indi-
cated in the operation sections of the specifications is not
implied. Exposure to Absolute Maximum Rating conditions
for extended periods my affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Total Supply Voltage (V
DD
to V
SS
) ....................... +18V
Input Voltage .................... (V
DD
+0.3V) to (V
SS
– 0.3V)
Storage Temperature Range.............. -65°C to +150°C
Voltage on Oscillator Control Pins...............V
DD
to V
SS
Duration of Output Short Circuit .....................Indefinite
Current Into Any Pin............................................ 10mA
While Operating (Note
3)............................100µA
Package Power Dissipation (T
A
70°C)
8-Pin Plastic DIP ....................................... 730mW
14-Pin Plastic DIP ..................................... 800mW
Operating Temperature Range
C Device .......................................... 0°C to +70°C
TC7652 ELECTRICAL SPECIFICATIONS
Electrical Characteristics:
V
DD
= +5V, V
SS
= -5V, C
A
= C
B
= 0.1F, T
A
= +25°C, unless otherwise indicated.
Symbol
Input
V
OS
V
OS
/T
Input Offset Voltage
Input Offset Voltage Average
Temperature Coefficient
Offset Voltage vs. Time
I
BIAS
Input Bias Current
—
—
—
—
—
—
—
—
—
—
—
-5
120
±0.7
±1.0
0.01
100
1.5
35
100
0.5
2
0.01
Parameter
Min.
Typ
Max
Units
Test Conditions
±5
—
0.05
—
10
150
400
—
—
—
—
V
V/°C
nV/
month
pA
pA
pA
pA
V
P-P
pA/Hz
T
A
= +25°C
Over Operating Temp Range
Operating Temperature Range
T
A
= +25°C
0°C
T
A
+70°C
-25°C
T
A
+85°C
R
S
= 100, 0 to 10Hz
f = 10Hz
I
OS
e
NP-P
I
N
R
IN
CMVR
CMRR
Output
A
V
OUT
Input Offset Current
Input Noise Voltage
Input Noise Current
Input Resistance
Common Mode Voltage Range
Common Mode Rejection Ratio
10
12
-5.2 to +2
130
+1.6
—
V
dB
CMVR = -5V to +1.5V
Large Signal Voltage Gain
Output Voltage Swing (Note
2)
Clamp ON Current
Clamp OFF Current
120
±4.7
—
25
—
130
±4.85
±4.95
70
1
—
—
—
200
—
dB
V
V
R
L
= 10k
R
L
= 10k
R
L
= 100k
R
L
= 100k (Note
1)
-4V < V
OUT
< +4V (Note
1)
Unity Gain (+1)
C
L
= 50pF, R
L
= 10k
A
pA
Dynamic
B
W
S
R
t
R
f
CH
Supply
V
DD
, V
SS
I
S
PSRR
Note
1:
2:
3:
Operating Supply Range
Supply Current
Power Supply Rejection Ratio
4.5
—
120
—
2
130
16
3.5
V
mA
dB
No Load
V
S
= ±3V to ±8V
Unity Gain Bandwidth
Slew Rate
Rise Time
Overshoot
Internal Chopping Frequency
—
—
—
—
120
2.0
2.5
0.2
20
200
—
—
—
—
375
MHz
V/sec
sec
%
Hz
Pins 12–14 Open (DIP)
See "Output Clamp" discussion.
Output clamp not connected. See typical characteristics curves for output swing versus clamp current characteristics.
Limiting input current to 100A is recommended to avoid latch-up problems.
2001-2012 Microchip Technology Inc.
DS21463C-page 3
TC7650
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Symbol
Description
Nulling capacitor pins
Inverting Input
Non-inverting Input
Negative Power Supply
Output Voltage Clamp
Output
Positive Power Supply
No internal connection
Capacitor current return pin
External Clock Input
Select Internal or External Clock
After the nulling amplifier is zeroed, the main amplifier
is zeroed; the A switches open and B switches close.
The output voltage equation is:
Pin Number
8-pin DIP
1,8
2
3
4
5
6
7
—
—
—
—
—
14-pin DIP
2,1
4
5
7
9
10
11
3,6
8
12
13
14
C
A
, C
B
-INPUT
+INPUT
V
SS
OUTPUT
CLAMP
OUTPUT
V
DD
NC
C
RETN
EXT CLK IN
INT/EXT
INT CLK OUT Internal Clock Output
3.0
3.1
DETAILED DESCRIPTION
Theory of Operation
Figure 3-1 shows the major elements of the TC7650.
There are two amplifiers (the main amplifier and the
nulling amplifier), and both have offset null capability.
The main amplifier is connected full-time from the input
to the output. The nulling amplifier, under the control of
the chopping frequency oscillator and clock circuit,
alternately nulls itself and the main amplifier. Two exter-
nal capacitors provide the required storage of the null-
ing potentials and the necessary nulling loop time
constants. The nulling arrangement operates over the
full common mode and power supply ranges, and is
also independent of the output level, thus giving excep-
tionally high CMRR, PSRR and A
VOL
.
Careful balancing of the input switches minimizes
chopper frequency charge injection at the input termi-
nals, and the feed forward type injection into the com-
pensation capacitor that can cause output spikes in this
type of circuit.
The circuit's offset voltage compensation is easily
shown. With the nulling inputs shorted, a voltage
almost identical to the nulling amplifier offset voltage is
stored on C
A
. The effective offset voltage at the null
amplifier input is:
EQUATION 3-2:
V
OUT
= A
M
V
OSM
+ (V
+
- V
-
) + A
N
(V
+
- V
-
) + A
N
V
OSE
EQUATION 3-3:
V OSM + V OSN
+
-
V OUT = A M A N
V
–
V
+ ------------------------------------------
-
AN
As desired, the device offset voltages are reduced by
the high open loop gain of the nulling amplifier.
3.2
Output Stage/Loading
EQUATION 3-1:
1
V OSE = ----------------- V OSN
-
A +1
N
The output circuit is a high impedance stage (approxi-
mately 18k). With loads less than this, the chopper
amplifier behaves in some ways like a trans-conduc-
tance amplifier whose open-loop gain is proportional to
load resistance. For example, the open loop gain will
be 17dB lower with a 1k load than with a 10k load.
If the amplifier is used strictly for DC, the lower gain is
of little consequence, since the DC gain is typically
greater than 120dB, even with a 1k load. In wideband
applications, the best frequency response will be
achieved with a load resistor of 10k or higher. This
results in a smooth 6dB/octave response from 0.1Hz to
2MHz, with phase shifts of less than 10° in the transi-
DS21463C-page 4
2001-2012 Microchip Technology Inc.
TC7650
tion region, where the main amplifier takes over from
the null amplifier. The clock frequency sets the transi-
tion region.
ing sum and difference frequencies, and causing dis-
turbances to the gain and phase versus frequency
characteristics near the chopping frequency. These
effects are substantially reduced in the TC7650 by
feeding the nulling circuit with a dynamic current corre-
sponding to the compensation capacitor current in such
a way as to cancel that portion of the input signal due
to a finite AC gain. The intermodulation and gain/phase
disturbances are held to very low values, and can gen-
erally be ignored.
3.3
Intermodulation
Previous chopper stabilized amplifiers have suffered
from intermodulation effects between the chopper fre-
quency and input signals. These arise because the
finite AC gain of the amplifier results in a small AC sig-
nal at the input. This is seen by the zeroing circuit as an
error signal, which is chopped and fed back, thus inject-
FIGURE 3-1:
TC7650 CONTAINS A NULLING AND MAIN AMPLIFIER. OFFSET CORRECTION
VOLTAGES ARE STORED ON TWO EXTERNAL CAPACITORS
.
V+
Analog Input
V-
B
+
Null
-
Main
Amplifier
V
OUT
Gain = A
M
TC7650
+
A
Null
-
Null
Amplifier
B
A
C
B
C
A
Gain = A
N
, Offset = V
OSN
FIGURE 3-2:
V
DD
V
SS
4
11
-
7
1
8
8
2
C
A
C
B
1
C
A
8-PIN PACKAGE
2
10
3
NULLING CAPACITOR
CONNECTION
V
DD
7
6
4
C
B
V
SS
3.5
Clock Operation
-
TC7650
5
+
TC7650
+
The internal oscillator is set for a 200Hz nominal chop-
ping frequency on both the 8- and 14-pin DIPs. With the
14-pin DIP TC7650, the 200 Hz internal chopping fre-
quency is available at the internal clock output (Pin 12).
A 400Hz nominal signal will be present at the external
clock input pin (Pin 13) with INT/EXT high or open. This
is the internal clock signal before a divide-by-two oper-
ation.
The 14-pin DIP device can be driven by an external
clock. The INT/EXT input (Pin 14) has an internal pull-
up and may be left open for internal clock operation. If
an external clock is used, INT/EXT must be tied to V
SS
(Pin 7) to disable the internal clock. The external clock
signal is applied to the external clock input (Pin 13).
The external clock amplitude should swing between
V
DD
and ground for power supplies up to ±6V and
between V
+
and V
+
-6V for higher supply voltages.
At low frequencies the external clock duty cycle is not
critical, since an internal divide-by-two gives the
desired 50% switching duty cycle. The offset storage
correction capacitors are charged only when the exter-
nal clock input is high. A 50% to 80% external clock
14-PIN PACKAGE
3.4
Nulling Capacitor Connection
The offset voltage correction capacitors are connected
to C
A
and C
B
. The common capacitor connection is
made to V
SS
(Pin 4) on the 8-pin packages and to
capacitor return (C
RETN
, Pin 8) on the 14-pin packages.
The common connection should be made through a
separate PC trace or wire to avoid voltage drops. The
capacitors outside foil, if possible, should be connected
to C
RETN
or V
SS
.
2001-2012 Microchip Technology Inc.
DS21463C-page 5
Analog electronics
京公网安备 11010802033920号
EEWORLD
