CY7C1051DV33
8-Mbit (512 K × 16) Static RAM
8-Mbit (512K x 16) Static RAM
Features
■
Functional Description
The CY7C1051DV33 is a high performance CMOS Static RAM
organized as 512 K words by 16-bits.
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data
from I/O pins (I/O
0
–I/O
7
), is written into the location specified on
the address pins (A
0
–A
18
). If Byte HIGH Enable (BHE) is LOW,
then data from I/O pins (I/O
8
–I/O
15
) is written into the location
specified on the address pins (A
0
–A
18
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte LOW Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O
0
–I/O
7
. If
Byte HIGH Enable (BHE) is LOW, then data from memory
appears on I/O
8
to I/O
15
. See the
Truth Table
on page 10 for a
complete description of read and write modes.
The input/output pins (I/O
0
–I/O
15
) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or a write operation (CE LOW, and
WE LOW) is in progress.
The CY7C1051DV33 is available in a 44-pin TSOP II package
with center power and ground (revolutionary) pinout and a
48-ball FBGA package.
For a complete list of related documentation,click
here.
Temperature ranges
❐
–40 °C to 85 °C
High speed
❐
t
AA
= 10 ns
Low active power
❐
I
CC
= 110 mA at f = 100 MHz
Low CMOS standby power
❐
I
SB2
= 20 mA
2.0-V data retention
Automatic power-down when deselected
Transistor-transistor logic (TTL)-compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in Pb-free 48-ball fine ball grid array (FBGA) and
44-pin thin small outline package (TSOP) II packages
■
■
■
■
■
■
■
■
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
SENSE AMPS
512 K × 16
ARRAY
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN
DECODER
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 001-00063 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 16, 2015
CY7C1051DV33
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 4
Thermal Resistance .......................................................... 4
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 5
Data Retention Waveform ................................................ 5
AC Switching Characteristics ......................................... 6
Switching Waveforms ...................................................... 7
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC® Solutions ...................................................... 15
Cypress Developer Community ................................. 15
Technical Support ..................................................... 15
Document Number: 001-00063 Rev. *J
Page 2 of 15
CY7C1051DV33
Pin Configurations
Figure 1. Pin Diagram - 48-ball FBGA (Top View)
[1]
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
A
18
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
V
CC
V
SS
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
Figure 2. Pin Diagram - 44-Pin TSOP II (Top View)
[1]
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
17
A
16
A
15
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
A
18
A
14
A
13
A
12
A
11
A
10
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
–10
10
110
20
–12
12
100
20
Unit
ns
mA
mA
\
Note
1. NC pins are not connected on the die.
Document Number: 001-00063 Rev. *J
Page 3 of 15
CY7C1051DV33
Maximum Ratings
Exceeding the maximum ratings may shorten the useful life of
the device. These user guidelines are not tested.
Storage temperature ................................ –65
C
to +150
C
Ambient temperature with
power applied............................................ –55
C
to +125
C
Supply voltage on V
CC
to relative GND
[2]
Static discharge voltage............. ...............................>2001 V
(per MIL-STD-883, Method 3015)
Latch-up current ...................................................... >200 mA
Operating Range
Range
Industrial
Industrial
Ambient
Temperature
V
CC
Speed
10 ns
12 ns
–40
C
to +85
C
3.3 V
0.3 V
–40
C
to +85
C
3.3 V
0.3 V
.... –0.5 V to +4.6 V
DC voltage applied to outputs
in high-Z state
[2]
...................................–0.3 V to V
CC
+ 0.3 V
DC input voltage
[2]
...............................–0.3 V to V
CC
+ 0.3 V
Current into outputs (LOW) ..........................................20 mA
DC Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH[2]
V
IL[2]
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input leakage current
Output leakage current
V
CC
operating
supply current
Automatic CE power
down current —TTL
inputs
Automatic CE Power
Down Current —CMOS
Inputs
GND < V
IN
< V
CC
GND < V
OUT
< V
CC
, Output
Disabled
f = f
MAX
= 1/t
RC
Max V
CC
, CE > V
IH
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Max V
CC
, CE > V
CC
– 0.3 V,
V
IN
> V
CC
– 0.3 V or V
IN
< 0.3 V, f
=0
Test Conditions
Min V
CC
, I
OH
= –4.0 mA
Min V
CC
, I
OL
= 8.0 mA
–10
Min
2.4
–
2.0
–0.3
–1
–1
–
–
Max
–
0.4
V
CC
+ 0.3
0.8
+1
+1
110
40
Min
2.4
–
2.0
–0.3
–1
–1
–
–
–12
Max
–
0.4
V
CC
+ 0.3
0.8
+1
+1
100
35
Unit
V
V
V
V
A
A
mA
mA
I
SB2
–
20
–
20
mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
C
IN
C
OUT
Description
Input capacitance
I/O capacitance
Test Conditions
T
A
= 25C, f = 1 MHz, V
CC
= 3.3 V
Max
12
12
Unit
pF
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
JA
JC
Description
Thermal resistance
(Junction to ambient)
Thermal resistance
(Junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
FBGA
Package
28.31
11.4
TSOP II
Package
51.43
15.8
Unit
C/W
C/W
Note
2. V
IL(min)
= –2.0 V and V
IH(max)
= V
CC
+ 2.0 V for pulse durations of less than 20 ns.
Document Number: 001-00063 Rev. *J
Page 4 of 15
CY7C1051DV33
AC Test Loads and Waveforms
AC characteristics (except High-Z) are tested using the load conditions shown in
Figure 3
(a). High-Z characteristics are tested for
all speeds using the test load shown in
Figure 3
(c).
Figure 3. AC Test Loads and Waveforms
Z = 50
OUTPUT
50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
3.0 V
30 pF*
GND
Rise Time: 1 V/ns
ALL INPUT PULSES
90%
10%
90%
10%
1.5 V
(a)
(b)
Fall Time: 1 V/ns
High-Z Characteristics
3.3 V
OUTPUT
5 pF
R2
351
(c)
R 317
Data Retention Characteristics
Over the Operating Range
Parameter
V
DR
I
CCDR
t
CDR[4]
t
R[4]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
CC
= V
DR
= 2.0 V, CE > V
CC
– 0.3 V,
V
IN
> V
CC
– 0.3 V or V
IN
< 0.3 V
Conditions
[3]
Min
2.0
–
0
t
RC
Max
–
20
–
–
Unit
V
mA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
CE
3.0 V
t
CDR
V
DR
>
2 V
3.0 V
t
R
Notes
3. No inputs may exceed V
CC
+ 0.3 V
4. Full device operation requires linear V
CC
ramp from V
DR
to V
CC
(min) > 50
s
or stable at V
CC
(min) > 50
s.
Document Number: 001-00063 Rev. *J
Page 5 of 15
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